The first answer to this question What is the difference between a store queue and a store buffer clearly explains the difference between store buffer and store queue.
But I'm still a little fuzzy on how the store instruction uses the store buffer and store queue.
When the processor executes a simple store instruction. Did it go through the following steps:
Fetch the corresponding instruction from the I-Cache <--> decode <--> rename <--> dispatch to the memory access queue <--> the store instruction is issued to the memory access unit
From here, I'm a little confused.
The data at the address of the store instruction is written to the store queue.
When the store instruction is at the head of the ROB, it is committed, and the data can be written to the L1 cache(That is, in the write-back phase).
However, since writing back to the L1 cache takes an indeterminate time, in order to decouple the processor pipeline and the access pipeline, the write-back phase actually writes the data and address of the store instruction into the store buffer.
The data will then be written back from the store buffer to the L1 cache.
- Is the above process correct?
- What data is stored in the store buffer? How does he know when and where to write?
