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Let's say I have a simple add instruction which needs to add two numbers. I need one cycle too fetch the instruction, one cycle to decode it, two cycles to fetch the numbers, one cycle to add the two numbers and one cycle to write the outcome back. So for such instruction I need 6 cycles. If you search the internet, many sources say that addition needs just one cycle. Do they refer just to the execution time, or to the whole pipeline?

max steuerman
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    What architecture? What instruction set? What implementation? – access violation Nov 02 '22 at 13:05
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    It depends on the context but 1c is very likely to be the execution time only. – Margaret Bloom Nov 02 '22 at 15:56
  • Normally it means average throughput when executing a sequence of independent add instruction, or latency when executing a sequence of *dependent* add instructions (which read the result of the previous add). In a superscalar CPU, these are usually not the same thing. See also [How many CPU cycles are needed for each assembly instruction?](https://stackoverflow.com/a/44980899) and [What considerations go into predicting latency for operations on modern superscalar processors and how can I calculate them by hand?](https://stackoverflow.com/q/51607391) – Peter Cordes Nov 02 '22 at 22:13
  • And especially http://www.lighterra.com/papers/modernmicroprocessors/ - Modern Microprocessors A 90-Minute Guide! is excellent. – Peter Cordes Nov 02 '22 at 22:13

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