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I was reading about 32-bit PCI bus and how a PCI device advances its address. AD[31:0] is used to for addresses and data. If the PCI is requesting all four bytes to be transferred at the same time, then those four bytes will occupy all the lines including AD[1:0]. It means AD[1:0] cannot indicate how the target should advance the address during a multidata phase burst.

Use of AD[1:0] for memory transfers

Source: PCI Bus Demystified by Abbott

Google Books: https://www.google.com/books/edition/PCI_Bus_Demystified/tVfeqL5F1DwC?hl=en&gbpv=1&pg=PA27&printsec=frontcover

I have tried to understand it on my own and consulted the internet without any success.

PG1995
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    The first sentence says that two other signals are used to select which byte-within-word is accessed, so the address lines only need 4-byte granularity, for an aligned 4-byte chunk. That leaves the low 2 bits free (with the actual chunk address having them implicit zeros in that position). – Peter Cordes Nov 12 '22 at 09:41
  • Thank you for the reply but I'm sorry I'm still struggling. A 32-bit PCI could, in my view, could provide total addresses from 0 to (4GB-1), or 2^32. It needs all those 32 lines, i.e., AD[31:0]. Please have a look here: https://i.stack.imgur.com/O61vm.jpg . It shows a 32-bit memory with total of 2^32 addresses. In simple words, I do not understand how the PCI wouldn't need AD[1:0] during the address phase. I'd appreciate it if you could simplify your comment in form of an answer. – PG1995 Nov 12 '22 at 10:49
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    That diagram is kinda broken or misleading. When then they write `4GB-1`, they seem to mean the last doubleword (4-bytes) in an address-space of 2^32 **bytes**, not 2^32 **dwords**. So an actual address of 2^32 - 4 = 0xfffffffc. But since they're numbering dwords instead of giving byte addresses (0, 4, 8, 12, 16, 20, ...), it would be dword # 2^30-1. Or 1G-1. They included a *unit* (B for bytes) in the address (not just a scale prefix like G), which makes no sense because the earlier columns in the same row don't have a unit given. – Peter Cordes Nov 12 '22 at 11:07
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    TL:DR: It's a big stretch to interpret that diagram in any way that would make it not just plain wrong. Like I said, should be 1G - 1 if we're talking about dword indexes, i.e. the two 30 bits of the full address. It's totally normal for CPUs that require 4-byte aligned chunk addresses in a 32-bit address space to have the low 2 bits of things implicitly zero, for example MIPS branch target addresses ([How to Calculate Jump Target Address and Branch Target Address?](https://stackoverflow.com/q/6950230)), because instructions can only be in aligned 4-byte words (what x86 would call a dword) – Peter Cordes Nov 12 '22 at 11:11
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    PCI has three address spaces: IO, Memory and Configuration. IO is byte addressable, that's why we need all `AD[31:0]`. Memory and Configuration are DWORD addressable, this means the master is only allowed to request address like 0, 4, 8, 12, 16, .... So the lower two bits `AD[1:0]` are not necessary. PCI could have exploited this in two ways: 1) make the Memory/Config spaces bigger by specifying that the addressable unit is a DWORD a not a byte but that would be... odd; 2) it could reuse them. They went for the latter. Note that `C/BE#` are NOT used during the address phase so their presence – Margaret Bloom Nov 12 '22 at 19:43
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    is irrelevant to the purpose of `AD[1:0]`. If you can find a copy of the PCI 3.0 Specifications, I advice you to read them. They are very clear and concise. – Margaret Bloom Nov 12 '22 at 19:44
  • Thank you very much! @PeterCordes The diagram was drawn by me and I think I can it now where I was going wrong. PCI 32 addresses the memory as DWORDS like 0, 4, ,8, 12, ... as has been pointed out. – PG1995 Nov 13 '22 at 14:10
  • @MargaretBloom Thanks a lot! Your comment was really helpful to see where I was going wrong with it. Does PCI-64 also addressed memory as DWORDS like 0, 4, 8, 12, and so? Since PCI-64 is backward compatible with PCI-32 so I'd guess PCI-64 also addresses memory as DWORDS. Could you please confirm it? – PG1995 Nov 13 '22 at 14:12
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    @PG1995 `AD[2]` must be 0 during the address phase of a 64-bit transfer (only memory transfers can be 64-bit). So the a 64-bit master access addresses like 0,8,16,24,32,... . Quoting the specs: *The master initiating a 64-bit data transaction must use a double DWORD (Quadword or 8 byte) referenced address (AD[2] must be "0" during the address phase)* – Margaret Bloom Nov 13 '22 at 19:41
  • @MargaretBloom Thanks a lot! I've downloaded PCI 3.0 Specifications but it's a 300+ pages book! Anyway, one last question. AD[2] must be 0 during address phase of 64-bit memory transaction. Now there two sets AD[31:0] and AD[63:32], and C/BE[3:0] and C/BE[7:4] for the 64-bit PCI. Are AD[1:0] and AD[33:32] used during the address phase? Possibly a silly query but I wanted to clarify. Thanks for the patience. – PG1995 Nov 14 '22 at 12:34
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    @PG1995 I would need to brush up on PCI 64-bit, but Yes, I would expect so. – Margaret Bloom Nov 15 '22 at 08:06

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