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I have a processor. Some instruction sets are AND, ADD, ANDI, ADDI. These looks like same but they are not. Can I assign same opcode for looks like same instructions sets as follows screen shot:

Example of ISA
or sixth bit is enough to differentiate them?

In actual example of ISA, I have 13 instruction sets (AND, ADD, LD, ST, ANDI, ADDI, CMP, JUMP, JE, JA, JB, JBE, JAE). Because of size of instruction sets, I think number of opcode bits should be 4 bits and also all different instruction sets should have different opcode like ADD 0001, ADDI 0010, AND 0011, and ANDI 0100 etc.

Peter Cordes
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doqukan
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    Yes, as long as you can differentiate you can do whatever you want. You don't have to use simple binary opcode. – Jester Dec 08 '22 at 00:21
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    Classic MIPS has the same "opcode" field for most R-type instructions, differentiating them with the `funct` field. Same sort of idea here. – Peter Cordes Dec 08 '22 at 00:24

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Absolutely. Most CISC CPU assembly languages do this actually. I'll use 6502 Assembly x86 Assembly to illustrate, but it's certainly possible to write your own MIPS assembler that allows this.

    mov eax,[eax]  ;encoded as 8B 00
    mov eax,[ecx]  ;encoded as 8B 01
    mov eax,[edx]  ;encoded as 8B 02
    mov eax,[ebx]  ;encoded as 8B 03

All of these instructions load the eax register indirectly using another register as a pointer to memory. Which register is used depends on the pattern of bits. Not the best example, but it is a thing that many CPUs do.

EDIT: used x86 Assembly for the example now, which doesn't completely change the bytes when using different operation modes for this example.

puppydrum64
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  • All those different instructions have different opcode bytes. The question is talking about machine-code instructions that have the same "opcode" field but are differentiated by other bits in the instruction word. e.g. `add` vs. `addi`, if you look at the image they linked. – Peter Cordes Dec 08 '22 at 15:15
  • @PeterCordes Perhaps I misunderstood the question. I'll research a more relevant example but I feel like x86 does something like this with its Mod R/M table. – puppydrum64 Dec 08 '22 at 15:36
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    yeah, some x86 instructions share the same opcode byte, using the `/r` field as 3 extra bytes. [How to read the Intel Opcode notation](https://stackoverflow.com/a/53976236) / [x64 instruction encoding and the ModRM byte](https://stackoverflow.com/q/15511482). Mostly immediates, which is why we only have `add r/m, imm`, not `add reg, r/m, imm`, only the 186 form of `imul reg, r/m, imm` works like that, with a whole opcode to itself so it can use both fields of ModRM for non-immediate operands so it can be non-destructive, like AVX. – Peter Cordes Dec 08 '22 at 15:38