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I've seen in a couple of places (e.g. here) that x86 memory model has slightly stronger than pure acquire-release semantics.

What are the specific reordering constraints that x86 has that acquire-release doesn't?

Peter Cordes
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ledonter
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    A total store order (no IRIW reordering / disagreement) is a major one. [Will two atomic writes to different locations in different threads always be seen in the same order by other threads?](//stackoverflow.com/a/50679223) x86's memory model is program order + a store buffer with store-forwarding, with a total store order. The existence of a total order of stores might be the only difference. (Unless you want to get into the fact that ISO C++'s memory model doesn't depend on the existence of coherent cache at all, and makes guarantees based only on loads seeing stores -> happens-before) – Peter Cordes Jan 20 '23 at 11:03

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