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I am a bit confused on when/where to apply ISB/DMB instructions. On one hand it's portrayed that operations within the processor will always stay consistent on the otherhand it indicates things can be reordered.

Under what conditions should you use ISB/DMB instructions?

Lets consider some examples:

  1. Writing to a memory location and reading from it.

  2. Writing to a Peripheral which needs to be initialized in a particular order.

  3. Writing to a peripheral which controls something(ex GPIO control).

FourierFlux
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  • For many Cortex-m systems, these operations are not needed. Typically you need a cache, **AND** data dependencies between hardware reads and writes. The `ISB` is only used when you update code **AND** have a cache. See: [ARM use of dsb,dmb and isb](https://stackoverflow.com/questions/15491751/real-life-use-cases-of-barriers-dsb-dmb-isb-in-arm). The only reason they are on *many* Cortex-M system is for binary compatibility. An exception will be systems with a cache. – artless noise Mar 18 '23 at 11:40
  • arm makes cores not chips, what the chip vendor does with it and what timing or race condition requirements are with that chip vendor. exception perhaps being caches purchased from arm. So as pointed out in the above comment, it may not be needed. have been using arm cores for as long as there have been arm cores and not had to isb/dmb between peripheral accesses for example. – old_timer Mar 18 '23 at 16:47
  • can the core do anything out of order (loads and stores)(doubt it) but are their paths in the chip that can be out of order (yeah, some designs yes). – old_timer Mar 18 '23 at 16:48

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