environment
os: macos 12.6.3 (intel)
gnu make: 3.81
execute command: make -v
get:
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
This program built for i386-apple-darwin11.3.0
steps
The directory structure is as follows
./
├── Makefile
└── abc.c
There are only two files in the directory: Makefile
and abc.c
, where the abc.c
file is empty file and has no content
The content of the Makefile
is as follows:
test: abc.o
@echo 'execute test.'
clean:
$(RM) test abc.o
.PHONY: test clean
Then, execute command: make clean && make test
, It will output:
rm -f test abc.o
cc -c -o abc.o abc.c
execute test.
So, My question is, why does the make
command automatically execute the cc -c -o
command in the second line of output? Is this make
command default behavior?
I tried renaming the abc.c
file to abc.java
and executing the command again, which was output as I expected. My original intention was to check if the abc.o
file exists, if file not exist, throw an error or output something
I cannot simply describe this issue, so I don't know how to use Google search. Can you provide me with an official document link to explain this behavior, or are there parameters that can avoid this default behavior?