Multi-Cycle Pipeline implementation: why do we cancel the earlier WB when addressing the WAW hazard to handle the exception?

Question

I learned 'Computer Organization and Design' RISC-V version by Patterson and Hennessy and searched 'Multi-Cycle Pipeline' on the internet and find this helpful doc chap3_6

I have some questions about the WAW hazard in the 'doc chap3_6' above:

In the following excerpt

Solving the WAW hazard can be accomplished in two ways:

Stall an instruction that would "pass" another until after the earlier instruction reaches the MEM phase.

Cancel the WB phase of the earlier instruction.

Since pure WAW hazards are not common, either method works.

Does it mean that we drops the earlier instruction ( in the doc context, I think it refers to ADDD instruction)? This seems to be weird.

The second excerpt seems to mean that non-pure WAW can use either method. What does the term 'pure' mean ? Does 'pure' mean that adjacent writes to the same address without other instructions between the two writes? If so, it can use the second method which is the opposite of what the excerpt means.

Answer 1

The earlier instruction could still bypass-forward to something that reads it between its write and the next. Unless the CPU has checked that there are no such reads, it can't fully nop out the first instruction. Also, if the first instruction was a load from a bad address, it still needs to take a page fault exception for example. Or an FP math instruction could have side effects on the FP status register, or raise an exception if unmasked.

The earlier instruction is probably part-way through the pipeline when the later instruction is detected, and having more wiring to maybe NOP-out every other pipeline stage of would cost more power than it would save. An in-order pipeline can't fill the slot by replacing it with another instruction, so just do the minimum possible and cancel write-back for something like an FP mul that's followed by an FP mov to the same register.