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In 'Patterson and Hennessy, Computer Architecture: A Quantitative Approach' 6th ed book p136, it has the following sentences:

The page frame of the instruction’s address (36 = 48 - 12 bits) is sent to the instruction TLB (step 1). At the same time, the 12-bit page offset from the vir- tual address is sent to the instruction cache (step 2).Notice that for the eight-way associative instruction cache, 12 bits are needed for the cache address: 6 bits to index the cache plus 6 bits of block offset for the 64-byte block, so no aliases are possible.The previous versions of the i7 used a four-way set associative I-cache, meaning that a block corresponding to a virtual address could actually be in two different places in the cache, because the corresponding physical address could have either a 0 or 1 in this location. For instructions this did not pose a prob- lem because even if an instruction appeared in the cache in two different locations, the two versions must be the same. If such duplication, or aliasing, of data is allowed, the cache must be checked when the page map is changed, which is an infrequent event. Note that a very simple use of page coloring (see Appendix B, Section B.3) can eliminate the possibility of these aliases. If even-address virtual pages are mapped to even-address physical pages (and the same for odd pages), then these aliases can never occur because the low-order bit in the virtual and phys- ical page number will be identical.

part of 'Figure 2.25 The Intel i7 memory hierarchy and the steps in both instruction and data access.' from the book:

Q:

1.1 questions about the meaning of some sentences above:

Here 'four-way set associative' will not imply the stored data. So what does 'corresponding physical address could have either a 0 or 1 in this location' mean ? where is the 'location'?

Does 'a block corresponding to a virtual address' means the data block stored in the physical address mapped from the virtual address ?

1.2 From above, it seems that the 'four-way set associative' causes the 'alias'. But from this Q&A, I think it is the different mapping ('page map' in the above quote) that causes the alias. So how does 'four-way set associative' cause that 'a block corresponding to a virtual address could actually be in two different places in the cache'?

zg c
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  • Related: [Minimum associativity for a PIPT L1 cache to also be VIPT, accessing a set without translating the index to physical](https://stackoverflow.com/q/59279049) - if a cache isn't associative enough, you'd have "synonym" aliasing unless the OS did page-coloring so an extra bit of the physical address matches the virtual address. – Peter Cordes Jun 22 '23 at 12:07
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    BTW, not everyone knows what CAAQA stands for, same for other book names in your other questions. It would be much better to give the actual name of the book at least once, preferably with the authors last names at least. Or at least a link. In this case, CAAQA is Patterson and Hennessy, Computer Architecture: A Quantitative Approach, but in your other questions you've used book abbreviations I didn't recognize. – Peter Cordes Jun 22 '23 at 12:10
  • Thanks. After reading this [Q&A](https://stackoverflow.com/questions/46588219/virtually-indexed-physically-tagged-cache-synonym) referenced in your offered link, I searched 'VIPT alias' by adding the keyword 'VIPT' and found this useful [geeksforgeeks link](https://www.geeksforgeeks.org/virtually-indexed-physically-tagged-vipt-cache/) with intuitive images. And I think I understand the problem. Here assume that the LSB bit is bit 0. 1. 'either a 0 or 1' means the bit 12 can be 0/1 in virtual address. – zg c Jun 22 '23 at 15:03
  • 2. (Here use verilog syntax to represent number)'four-way' implies changing from 6 bit index to 7 bit. So `{{35{1'b0}},1'b1,{12{1'b0}}}` and `{{35{1'b0}},1'b0,{12{1'b0}}}` use different index (the former is `{1'b1,{6{1'b0}}}` while the latter is `{1'b0,{6{1'b0}}}`). But the `{{35{1'b0}},1'b1}` and `{{35{1'b0}},1'b0}` virtual tags **may** be mapped to the same physical tags by TLB. Then it results the "synonym" aliasing because two virtual addresses maps to same physical address. – zg c Jun 22 '23 at 15:16
  • comments added to the above 3rd comment: So the virtual address could be mapped to two optional physical address , implying that two virtual addresses may be mapped to the same physical address. Then the data block of the same physical address are duplicated (alias) in different cache locations. Are the above comments of mine right ? If not, please point out. Thanks. – zg c Jun 22 '23 at 15:32
  • Comments added to the above 3rd comment: Originally before asking the question , I seached somthing like 'cache alias' or 'duplication, or aliasing, of data cache'. When searching 'synonym aliasing cache', I found [intel doc](https://www.intel.com/content/www/us/en/docs/programmable/683836/current/virtual-address-aliasing.html). Although it says the same thing and can be understood after reading it , but maybe offering image can help the reader get the idea more quickly and easily. – zg c Jun 23 '23 at 00:30

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