Recently, I used perf to improve the program performance. It has two events l2_cache_req_stat.ls_rd_blk_cs and l2_cache_req_stat.ls_rd_blk_l_hit_s on my zen2 r7 4800h cpu. They can be seen in the source codes. But it may be better to view it in the 17h A0h PPR doc revision (This model may be very new and not included in wikichip cpuid when I posted. Although I use 17h 60h cpu, they are both zen2 17h family and used the same PMCx064) where AMD may give one more clear description about their differences.
the "Non-Modifiable" corresponds to "Shared" in MOESI which is used by AMD (this is also said in AMD64 Architecture Programmer’s Manual) and "Shared Read" probably includes one more state ("Owned"):
Bits Description
7 LsRdBlkCS: Data Cache Shared Read Hit in L2. Read-write. Reset: 0.
5 LsRdBlkLHitS: Data Cache Read Hit Non-Modifiable Line in L2. Read-write. Reset: 0.
If so, on the different PMCx060 from the above PMCx064, l2_cache_accesses_from_dc_misses ("L2 Cache Accesses from L1 Data Cache Misses (including prefetch)") don't have l2_request_g1.ls_rd_blk_c_s (Data cache shared reads) unit mask set.
Why does l2_cache_accesses_from_dc_misses not take l2_request_g1.ls_rd_blk_c_s in account?
