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I came across several references to the concept of a dual issue processor (I hope this even makes sense in a sentence). I can't find any explanation of what exactly dual issue is. Google gives me links to micro-controller specification, but the concept isn't explained anywhere. Here's an example of such reference. Am I looking in the wrong place? A brief paragraph on what it is would be very helpful.

pmod
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Phonon
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    I think the link you provided seems to talk about dual issue instructions rather than dual issue processors. It talks about what restrictions they have that would cause a second pipeline to be required in the next cycle. [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363e/Cegbbffb.html](this) is a link to another article for the R-series processor documentation that talks about (potentially different?) dual issue instructions more – Abdul Hfuda Nov 04 '11 at 19:42
  • http://electronics.stackexchange.com/questions/145473/single-issue-and-dual-issue-architecture – Ciro Santilli OurBigBook.com Apr 02 '16 at 09:19

1 Answers1

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Dual issue means that each clock cycle the processor can move two instructions from one stage of the pipeline to the next stage. Where this happens depends on the processor and the company's terminology: it can mean that two instructions are moved from a decode queue to a reordering queue (Intel calls this issue) or it could mean moving instructions (or micro-operations or something) from a reordering queue to an execution port (afaik IBM calls this issue, while Intel calls it dispatch)

But really broadly speaking it should usually mean you can sustain executing two instructions per cycle.

Since you tagged this ARM, I think they're using Intel's terminology. Cortex-A8 and Cortex-A9 can, each cycle, fetch two instructions (more in Thumb-2), decode two instructions, and "issue" two instructions. On Cortex-A8 there's no out of order execution, although I can't remember if there's still a decode queue that you issue to - if not you'd go straight from decoding instructions to inserting them into two execution pipelines. On Cortex-A9 there's an issue queue, so the decoded instructions are issued there - then the instructions are dispatched at up to 4 per cycle to the execution pipelines.

Björn Lindqvist
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Exophase
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    Of course ARM and Intel got it all wrong. The terms _dispatch_ and _issue_ go back all the way to the 60s and the CDC 6600. – Mackie Messer Nov 19 '11 at 23:29