How many number of machine cycles are required for the RET instruction in 8085?
Why does it require that many number of cycles?
How many number of machine cycles are required for the RET instruction in 8085?
Why does it require that many number of cycles?
The RET instruction needs 3 machine cycles. One to fetch and decode the instruction (4 T states), and two more machine cycles (that is, 2*3 = 6 T states) to read two bytes from the stack (stack is exterior to microprocessor, stack is in read-write memory, so to exchange data with stack needs machine cycles). Thus, the RET instruction needs a total of 3 machine cycles and 10 T-states.
Ref.: How many machine cycles are required for RET instruction in 8085 microprocessor is ? (sic).
The RET instruction takes 10 cycles, according to the table at this site: http://www.cavehill.uwi.edu/fpas/cmp/online/el21c/lesson18.html
The instruction requires 3 memory fetches, one for the opcode and 2 for the return address, with each fetch taking 3 cycles (or more if the memory requires wait states). The opcode decode takes one cycle more.