How can Makefile use separate directories for source code and binaries?

Question

I want to be able to split up my bin and my code files into separate directories as it is becoming hard to manage in it's current state.

I ideally would like to have

project_dir
|-Makefile
|-run_tests.sh
|
|__source
|  |-program1.cpp
|  |-program2.cpp
|
|__bin
   |-program1
   |-program2

However I am unable to get this to work with my current system without having to manually write out the rules for every program (bear in mind that every program is a separate program, not a series of objects linked together)

#Current make system
BIN=./bin/
SOURCE=./source/

LIST=program1 program2...

all: $(LIST)

%:  $(SOURCE)%.cpp
    $(CC) $(INC) $< $(CFLAGS) -o $(BIN)$@ $(LIBS)

this works except it I it can't see the target in the current path so it think it always rebuilds the binaries even if the source files haven't changed.

My only thought at the moment is to write a program to make a makefile but I don't want to do that.

The traditional approach is to call the source directory `src`, build the binaries in there, and have a separate step `install` in which the binaries are copied to the `bin` directory - there is even a special utility `install` to do that. — reinierpost, Feb 07 '12 at 19:23

score 29 · Accepted Answer · answered Feb 07 '12 at 14:56

29

You were almost there ...

#Current make system
BIN=./bin/
SOURCE=./source/

LIST=$(BIN)/program1 $(BIN)/program2...

all: $(LIST)

$(BIN)/%:  $(SOURCE)%.cpp
    $(CC) $(INC) $< $(CFLAGS) -o $@ $(LIBS)

You can also make the LIST easier by using the following

PROG=program1 program2
LIST=$(addprefix $(BIN)/, $(PROG))

answered Feb 07 '12 at 14:56

Didier Trosset

36,376
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Dumb question maybe but is there any way to use the '%' variable (ie name less directory) on the command line. so "gcc blah blah -D %" (so the program knows it's own name) – 111111 Feb 07 '12 at 15:17
3

Yes, you can use `$*` to get the stem. – Didier Trosset Feb 07 '12 at 15:17
Excellent I think my make file is about done, thanks for all your help. – 111111 Feb 07 '12 at 15:20
I just saw you added: 'addprefix', that is ever better, thanks again :) – 111111 Feb 08 '12 at 13:18

ArtificiallyIntelligence · Answer 2 · 2017-09-21T03:23:00.490

Here is a complete ready-to-go version of the Makefile.

Prepare your folder with the following directory

for .o files:/build/ for .cpp files: /src/ for binary files: /bin/

Then use the following Makefile at /

CC          = g++
LD          = g++ 
CFLAG       = -Wall
PROG_NAME   = prog

SRC_DIR     = ./src
BUILD_DIR   = ./build
BIN_DIR     = ./bin
SRC_LIST = $(wildcard $(SRC_DIR)/*.cpp)
OBJ_LIST = $(BUILD_DIR)/$(notdir $(SRC_LIST:.cpp=.o))

.PHONY: all clean $(PROG_NAME) compile

all: $(PROG_NAME)

compile: 
    $(CC) -c $(CFLAG) $(SRC_LIST) -o $(OBJ_LIST)

$(PROG_NAME): compile
    $(LD) $(OBJ_LIST) -o $(BIN_DIR)/$@

clean:
    rm -f $(BIN_DIR)/$(PROG_NAME) $(BUILD_DIR)/*.o

Your final program will be named as prog in the /bin/, everytime you compile the code, binaries will be separated at /build/ so that source code directory will be very neat and clean.

Your solution works but rebuilds everything which is a bit sad. — Gabriel Devillers, Nov 30 '18 at 20:16
This is not "a bit sad" but defies the entire purpose of using make. -1 — Przemek D, Feb 17 '21 at 11:45

score 2 · Answer 3 · answered Feb 07 '12 at 14:56

2

Easy solution: Use automake.

If you want to do this by hand, you'll need to employ the vpath directive or the VPATH environment variable. The GNU make manual has a section about them. Put your Makefile directly into the bin directory, set VPATH to the source directory, and implicit rules will work again.

answered Feb 07 '12 at 14:56

thiton

35,651
4
70
100

2

Not a fan of automake if it can be done with a well made make file. – 111111 Feb 07 '12 at 15:11
Upped for `vpath`; though, I wouldn't call autotools "easy". – Victor Sergienko Mar 20 '19 at 18:17

score 0 · Answer 4 · answered Mar 10 '23 at 12:27

I have the same case but in C code, and I've tried the solutions above, but no one was valid for me (on Mac OSX OS), so I tried other solutions also found in stackoverflow like: https://stackoverflow.com/a/53138757/2467917 and the result will be like below code (you need to make build folder at the same make file directory and feel free to change the other names of folders in variables to be suitable for your project):

MKDIR    = mkdir
RMDIR    = rm -rf
CC       = clang    
BIN      = build/bin
OBJ      = build/obj
INCLUDE  = include
SRC      = src
CFLAGS   = -Wall -g -I$(INCLUDE)
LDLIBS   = -lm
SRCS     = $(wildcard $(SRC)/*.c)
OBJS     = $(patsubst $(SRC)/%.c,$(OBJ)/%.o,$(SRCS))
EXE      = $(patsubst $(SRC)/%.c,$(BIN)/%.exe,$(SRCS))

.PHONY: all clean

all: $(EXE)

$(EXE): $(OBJS) | $(BIN)

# linker
$(BIN)/%.exe: $(OBJ)/%.o
    $(CC) $(LDFLAGS) $< -o $@ $(LDLIBS)

# compiler  
$(OBJ)/%.o: $(SRC)/%.c | $(OBJ)
    $(CC) $(CFLAGS) -c $< -o $@

$(BIN) $(OBJ):
    $(MKDIR) $@

clean:
    $(RMDIR) $(OBJ) $(BIN)

How can Makefile use separate directories for source code and binaries?

4 Answers4

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