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Hello I am currently working with a AT91SAM7X256 running on "bare metal". I have thoroughly read the datasheet as well as the architecture manual, with that in mind I came away with the conclusion that FIQ is higher priority than IRQs therefore FIQs should not be pre-empted by IRQs

However in practice I am noticing the IRQs suspend the execution of my FIQ handler even though I am not touching the F bit in the CPSR. Is it incorrect to assume that FIQs should not be suspended to service IRQs?

What do I need to do to make sure my FIQ service routine does not get interrupted?

Thanks you

maguirre
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1 Answers1

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When you enter an FIQ handler, ARM core automatically disables further interrupts, both FIQ and IRQ, by setting the 'I' and 'F' bits in the CPSR. This gives you a feel that nothing can pre-empt an FIQ. But SW can override this behavior! So I guess some part of your code is touching the CPSR and resetting the 'I' bit. And hence IRQ interrupts might be getting triggered even when your FIQ is running.

To add to the above explanation, the reason FIQs seem special is that when an IRQ handler is entered only the 'I' bit is set there by disabling only further IRQs. 'F' bit is not set and hence further FIQs can interrupt a running IRQ handler without the need of SW intervention.

Pavan Manjunath
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