passing strings to a make file

Question

I would like to do the following. I don't know whether it's possible to do it. If possible I would like to know how to do it.

make VAR1=arg1,arg2,arg3

based on the arg I would like to pass a switch to gcc.

For example,

if arg1 and arg2 are passed I would like to define a switch and if arg2 and arg3 are passed I would like to define another switch in the make file. How do I do that?

score 0 · Answer 1 · edited May 23 '17 at 10:08

0

Did you check GMSL?

http://gmsl.sourceforge.net/

conditional-directive
text-if-true
endif

https://stackoverflow.com/a/180818/643500

...

if you want to pass it seperated by commas, then you can split the string and pass it to the if statements.

edited May 23 '17 at 10:08

Community

1
1

answered Mar 30 '12 at 21:46

Sully

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score 0 · Accepted Answer · answered Apr 02 '12 at 12:32

Use make VAR1="arg1 arg2 arg3" with this in the makefile:

ifeq (arg1 arg2,$(findstring arg1,$(VAR1)) $(findstring arg2,$(VAR1)))
# define a switch
endif

ifeq (arg2 arg3,$(findstring arg2,$(VAR1)) $(findstring arg3,$(VAR1)))
# define another switch
endif

If there are a lot of these switches, you can define a macro to simplify the makefile.

passing strings to a make file

2 Answers2