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Questions tagged [coalescing]

49 questions
25
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2 answers

How to write a proper null-safe coalescing operator in scala?

Having seen the answers coming out of questions like this one involving horror shows like trying to catch the NPE and dredge the mangled name out of the stack trace, I am asking this question so I can answer it. Comments or further improvements…
psp
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null coalescing issue with abstract base/derived classes

Why is the C# null coalescing operator not able to figure this out? Cat c = new Cat(); Dog d = null; Animal a = d ?? c; This will give the error Operator ?? cannot be applied to operands of type Dog and Cat It just seems strange given the…
user1054637
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CUDA coalesced access to global memory

I have read CUDA programming guide, but i missed one thing. Let's say that i have array of 32bit int in global memory and i want to copy it to shared memory with coalesced access. Global array has indexes from 0 to 1024, and let's say i have 4…
Hlavson
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8
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CUDA programming - L1 and L2 caches

Could you please explain the differences between using both "L1 and L2" caches or "only L2" cache in CUDA programming? What should I expect in time execution? When could I expect smaller gpu time? When I enable both L1 and L2 caches or just enable…
Saman I
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7
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2 answers

Lazily coalesce Options in Scala

I have several ways of calculating a value, in decreasing preference. firstWay() second() + way() orA(thirdWay()) Each of these returns an Option. I want to "coalesce" these and get an Option which the the value returned by the first Some of these,…
Paul Draper
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5
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2 answers

Memory Coalescing vs. Vectorized Memory Access

I am trying to understand the relationship between memory coalescing on NVIDIA GPUs/CUDA and vectorized memory access on x86-SSE/C++. It is my understanding that: Memory coalescing is a run-time optimization of the memory controller (implemented…
Matthias Springer
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2 answers

CUDA - Coalescing memory accesses and bus width

So the idea that I have about coalescing memory accesses in CUDA is, that threads in a warp should access contiguous memory addresses, as that will only cause a single memory transaction (the values on each address are then broadcast to the threads)…
Alexandre Dias
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4
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How can I use coalescing operator in Haxe?

As I mentioned in the question, How can I use coalescing operator in Haxe?
Enes F.
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1 answer

How can you cause a javascript Object to be treated as falsy?

The use case I'm considering is creating a hopelessly egocentric Null for coalescing. This code works but requires an explicit check against the Null in question: const Null = new Proxy({}, {get: () => Null}); let data =…
david
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OpenCl matrix transposition with memory coalescing

I´m currently trying to transpose a Matrix in OpenCl with memory coalescing. I've already tansposed the Matrix in a "simple" way which worked perfectly fine. When I tried to do the same thing now with memory coalescing, i was hoping to see a little…
MiepMiep
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3
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1 answer

Does vector involves coalescing vector elements?

As stated in the subject: does vector involves coalescing vector elements in the same way of vector?
grd
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4 answers

C# coalescing operator with 3 possible return values?

Just reading up on the specs for this operator ?? as it takes the left side and, if null returns the value on the right side. My question is, can I have it return 3 possible values instead? Something like this: int? y = null; int z = 2; int x = y…
Solomon Closson
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Null coalescing operator on decimal and decimal

I'm facing the following error while applying a null coalescing operator. private decimal _currentImpulseId; // ... later on used in public property getter as follows public decimal CurrentImpulseId { get { return _currentImpulseId ?? 0M; } set…
Jens
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What is faster in CUDA: global memory write + __threadfence() or atomicExch() to global memory?

Assuming that we have lots of threads that will access global memory sequentially, which option performs faster in the overall? I'm in doubt because __threadfence() takes into account all shared and global memory writes but the writes are coalesced.…
dsilva.vinicius
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GPGPU - CUDA: global store efficiency

I am trying to figure out how well the global memory write accesses of one of my kernels are coalesced, based on the "global store efficiency" value of NVidia's profiler (I am using CUDA 5 toolkit preview release, on a Fermi GPU). As far as I…
Bids
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