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Questions tagged [instructions]

Questions about instructions of real CPUs, VMs or compiler IRs.

Questions about instructions of real CPUs such as ARM and x86, virtual machines such as Java, or compiler internal representations such as LLVM.

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Why do ARM chips have an instruction with Javascript in the name (FJCVTZS)?

FJCVTZS is "Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero". It is supported in Arm v8.3-A chips and later. Which is odd, because you don't expect to see JavaScript so close to the bare metal. I can find explanations…
Tim Smith
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`testl` eax against eax?

I am trying to understand some assembly. The assembly as follows, I am interested in the testl line: 000319df 8b4508 movl 0x08(%ebp), %eax 000319e2 8b4004 movl 0x04(%eax), %eax 000319e5 85c0 testl %eax, %eax …
maxpenguin
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Are there any smart cases of runtime code modification?

Can you think of any legitimate (smart) uses for runtime code modification (program modifying it's own code at runtime)? Modern operating systems seem to frown upon programs that do this since this technique has been used by viruses to avoid…
deo
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What does the endbr64 instruction actually do?

I've been trying to understand assembly language code generated by GCC and frequently encounter this instruction at the start of many functions including _start(), but couldn't find any guide explaining its purpose: 31-0000000000001040 <_start>: 32:…
Mah35h
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C code loop performance [continued]

This question continues on my question here (on the advice of Mystical): C code loop performance Continuing on my question, when i use packed instructions instead of scalar instructions the code using intrinsics would look very similar: for(int…
Ricky
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How does x86 pause instruction work in spinlock *and* can it be used in other scenarios?

The pause instruction is commonly used in the loop of testing spinlock, when some other thread owns the spinlock, to mitigate the tight loop. It's said that it is equivalent to some NOP instructions. Could somebody tell me how exactly it works for…
Infinite
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C code loop performance

I have a multiply-add kernel inside my application and I want to increase its performance. I use an Intel Core i7-960 (3.2 GHz clock) and have already manually implemented the kernel using SSE intrinsics as follows: for(int i=0; i
Ricky
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Difference between movq and movabsq in x86-64

I'm talking about data movement instructions in the x86-64 Intel architecture. I have read that the regular movq instruction can only have immediate source operands that can be represented as 32-bit two's complement numbers, while the movabsq…
IgNite
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IL Instructions not exposed by C#

What IL instructions are not exposed by C#? I'm referring to instructions like sizeof and cpblk - there's no class or command that executes these instructions (sizeof in C# is computed at compile time, not at runtime AFAIK). Others? EDIT: The reason…
YellPika
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What is the 0x10 in the "leal 0x10(%ebx), %eax" x86 assembly instruction?

What the function is of the 0x10 in regards to this LEAL instruction? Is it a multiply or addition or is something else? leal 0x10(%ebx), %eax Can someone please clarify? This is x86 assembler on a Linux box.
Tony The Lion
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MOVing between two memory addresses

I'm trying to learn assembly (so bear with me) and I'm getting a compile error on this line: mov byte [t_last], [t_cur] The error is error: invalid combination of opcode and operands I suspect that the cause of this error is simply that its not…
Justin
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How is x86 instruction cache synchronized?

I like examples, so I wrote a bit of self-modifying code in c... #include #include // linux int main(void) { unsigned char *c = mmap(NULL, 7, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE| …
Will
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JVM instruction ALOAD_0 in the 'main' method points to 'args' instead of 'this'?

I am trying to implement a subset of Java for an academic study. Well, I'm in the last stages (code generation) and I wrote a rather simple program to see how method arguments are handled: class Main { public static void main(String[] args) { …
ArjunShankar
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Why can an executable run on both Intel and AMD processors?

How is it that an executable can work on both AMD and Intel systems? Aren't AMD's and Intel's instruction sets different? How does the executable work on both? How exactly do they compile the files to work like that? And what exactly is the role of…
RahulCastro
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What are the semantics of ADRP and ADRL instructions in ARM assembly?

ADRP Address of 4KB page at a PC-relative offset. ADRL Load a PC-relative address into a register. It is similar to the ADR instruction. ADRL can load a wider range of addresses than ADR because it generates two data processing…
sherlock
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