Stack Overflow
Stack Overflow

Questions tagged [intel-mic]

Intel Many Integrated Core Architecture

Intel MIC (Intel Many Integrated Core Architecture) is a coprocessor computer architecture developed by Intel and used in Intel Xeon Phi processor product family.

More information

66 questions
19
votes
1 answer

Running Haskell on Xeon-Phi

Is there a way to compile Haskell to run on the Xeon Phi coprocessor? Some researchers at Intel have recently reported on the Haskell Research Compiler (that is not publicly available, which makes their results essentially irreproducible) and…
jev
  • 2,023
  • 1
  • 17
  • 26
18
votes
2 answers

Is the Intel Xeon Phi usable without a costly Intel Compiler?

Does the Intel Xeon Phi coprocessor, to be usable as parallel platform, require a license of the Intel Composer XE compiler, or are there alternative compilers?
clstaudt
  • 21,436
  • 45
  • 156
  • 239
17
votes
1 answer

How do the Conflict Detection instructions make it easier to vectorize loops?

The AVX512CD instruction families are: VPCONFLICT, VPLZCNT and VPBROADCASTM. The Wikipedia section about these instruction says: The instructions in AVX-512 conflict detection (AVX-512CD) are designed to help efficiently calculate conflict-free…
zr.
  • 7,528
  • 11
  • 50
  • 84
12
votes
1 answer

Can't force inlining C++ function using Intel compiler

I have a function defined as inline void vec_add(__m512d &v3, const __m512d &v1, const __m512d &v2) { v3 = _mm512_add_pd(v1, v2); } (the __m512d is a native data type mapping to SIMD registers on Intel MIC architecture) As this function is…
lei_z
  • 1,049
  • 2
  • 13
  • 27
9
votes
2 answers

Fast popcount on Intel Xeon Phi

I'm implementing an ultra fast popcount on Intel Xeon® Phi®, as it's a performance hotspot of various bioinformatics software. I've implemented five pieces of code, #if defined(__MIC__) #include __attribute__((align(64))) static const…
Aquaskyline
  • 93
  • 6
7
votes
1 answer

Are there SIMD(SSE / AVX) instructions in the x86-compatible accelerators Intel Xeon Phi?

Are there SIMD(SSE / AVX) instructions in the x86-compatible accelerators MIC Intel Xeon Phi? http://en.wikipedia.org/wiki/Xeon_Phi
Alex
  • 12,578
  • 15
  • 99
  • 195
7
votes
2 answers

Assembly syntax for masked vector Intel AVX-512 instructions

For testing purposes, I am writing short assembly snippets for Intel's Xeon Phi with the Icc inline assembler. Now I wanted to use masked vector instructions, but I fail at feeding them to the inline assembler. For code like this: vmovapd …
user116429
  • 131
  • 7
6
votes
2 answers

Is there a simulator/emulator of Xeon Phi?

I am going to offload some computation to Xeon Phi but would like to test different APIs and different apporached to the parallel programming first. Is there a simulator / emulator for Xeon Phi (either Windows or Linux) ?
Boppity Bop
  • 9,613
  • 13
  • 72
  • 151
6
votes
2 answers

MKL Performance on Intel Phi

I have a routine that performs a few MKL calls on small matrices (50-100 x 1000 elements) to fit a model, which I then call for different models. In pseudo-code: double doModelFit(int model, ...) { ... while( !done ) { cblas_dgemm(...); …
Andrew
  • 867
  • 7
  • 20
5
votes
1 answer

Get specific model of a xeon phi

I'm trying to find the exact model of a Xeon Phi coprocessor i'm using. I run micpinfo and this is what i get ***************************/opt/intel/mic/bin/micinfo*************************** MicInfo Utility Log Created Fri Jan 10 13:09:40…
user1730250
  • 582
  • 2
  • 9
  • 26
4
votes
3 answers

Offload daemon on xeon phi 5110p

I am aware that the Intel Xeon phi coprocessor SE10X has 61 cores and it is suggested to use only 60 cores since 1 core is used for the offload daemon. Also, since intel xeon phi coprocessor 5110P has 60 cores, is it suggested to use 59 cores?
hrs
  • 487
  • 5
  • 18
4
votes
2 answers

Device not available error when running code on Intel MIC

When I try to run my code on Intel MIC it is giving an error like "offload error: cannot offload to MIC - device is not available" My sample code is #include #include int main() { int N=10; int i, a[N]; #pragma offload…
user1495695
  • 41
  • 3
3
votes
1 answer

Required time to offload a function to Intel Xeon Phi

Is there a predefined time that is required for offload call to transfer the data(parameters) of a function from host to Intel MIC(Xeon Phi coprocessor 3120 series)? Specifically I do offload call ("#pragma offload target(mic)") for a function that…
wasilis
  • 115
  • 1
  • 8
3
votes
0 answers

Will _mm512_mask_prefetch_i32gather_ps() prefetch an entire cache line for each element?

The gather prefetch intrinsic _mm512_mask_prefetch_i32gather_ps can be used to prefetch 32 bit floats on Knights Corner. Since a corresponding intrinsic for doubles does not exist, how should this intrinsic be used for prefetch 64 or 128 bit…
amckinley
  • 629
  • 1
  • 7
  • 15
3
votes
0 answers

Why are the timings for the vectorized reduction for a simple Riemann sum-integral on Xeon Phi so bad?

I am new to the Xeon Phi and so I am going through the manuals trying to understand how to improve performance on the Phi using the vector registers. Consider the short code at the end of this question which calculates the area under the curve…
smilingbuddha
  • 14,334
  • 33
  • 112
  • 189
1
2 3 4 5