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Questions tagged [knights-landing]

Knights Landing is the name applied to Intel's second generation Xeon Phi product family. Use this tag when you have question specific to running on one of these processors.

The second generation Xeon Phi product family is known as "Knights Landing". It was launched in 2016 and has since been discontinued by Intel. They feature 64 to 72 cores with base frequencies ranging from 1.3GHz to 1.5GHz.

List of Knights Landing products from Intel

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What is the most efficient way to clear a single or a few ZMM registers on Knights Landing?

Say, I want to clear 4 zmm registers. Will the following code provide the fastest speed? vpxorq zmm0, zmm0, zmm0 vpxorq zmm1, zmm1, zmm1 vpxorq zmm2, zmm2, zmm2 vpxorq zmm3, zmm3, zmm3 On AVX2, if I wanted to clear ymm registers, vpxor was…
Maxim Masiutin
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What is _kmp_fork_barrier and how to see if there is load imbalance?

I'm using Intel VTune Amplifier to see how my parallel application scales. Notice I don't use any explicit lock mechanism It scales pretty well on my 4-cores laptop (considering that there are portions of the algorithm that can't be…
cplusplusuberalles
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adding "-march=native" intel compiler flag to the compilation line leads to a floating point exception on KNL

I have a code, which i launch on Intel Xeon Phi Knights Landing (KNL) 7210 (64 cores) processor (it is a PC, in native mode) and use the Intel c++ compiler (icpc) version 17.0.4. Also i launch the same code on Intel core i7 processor, where the…
And
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Can I compile Go programs on Xeon Phi (Knight's Landing) processors?

I'm a hobbyist who likes to run my own programs in Go, and as Xeon Phi processors become older they're also becoming extremely cheap. So cheap I can build a dual socket machine from 2015/16 for <$1000 I'm trying to find out if I can run Go programs…
haxonek
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Memory access error with _mm512_i64gather_pd()

I am trying to use a very simple example of the AVX-512 gather instructions: double __attribute__((aligned(64))) array3[17] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, …
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Convert array of eight bytes to eight integers

I am working with the Xeon Phi Knights Landing. I need to do a gather operation from an array of doubles. The list of indices comes from an array of chars. The gather operations are either _mm512_i32gather_pd or _mm512_i64gather_pd. As I understand…
Z boson
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available threads in Knights Landing

I am programming on a Knights Landing node which has 68 cores and 4 hyperthreads/core. I am working on a hybrid MPI/OpenMP application. My question is if the 4 hyperthreads are meant to be used as OpenMP threads or how could I use them? When I run…
armando
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How to detect a Xeon Phi (Knights Landing)

Intel engineers wrote that we should use VZEROUPPER/VZEROALL to avoid costly transition to non-VEX state on all processors, including future Xeon processor, but not on Xeon Phi: https://software.intel.com/pt-br/node/704023 People have also measured…
Maxim Masiutin
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Sobel Filter (OpenMP implementation)

I am trying to implement a parallelized + vectorized version of Sobel Filter in C with OpenMP pragmas for the paralleization and #pragma simd for vectorization. My input is a .pgm image of 1024 by 1024. I am compiling this using Intel Compiler on a…
lovetolearn
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Do the Airmont cores on Knight's Landing Xeon Phi's support SIMD instructions?

According to the source of the Wikipedia page on the Knight's Landing chip, it has Airmont cores. According to this page, those cores support SSE4.2 instructions, that is, SIMD instructions on SIMD registers. Is that really the case? If so, what's…
einpoklum
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