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Questions tagged [msr]

MSR (Model-Specific Registers) are registers inside the CPU that provide direct access to advanced CPU features.

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How can the L1, L2, L3 CPU caches be turned off on modern x86/amd64 chips?

Every modern high-performance CPU of the x86/x86_64 architecture has some hierarchy of data caches: L1, L2, and sometimes L3 (and L4 in very rare cases), and data loaded from/to main RAM is cached in some of them. Sometimes the programmer may want…
osgx
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Using GDB to read MSRs

Is there some way to read the x86-64 model-specific registers, specifically IA32_FS_BASE and IA32_GS_BASE, while debugging a program using GDB? Less preferable would be a solution using a dynamic instrumentation package like Intel's Pintool, but it…
shigoel
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Reading /dev/cpu/*/msr from userspace: operation not permitted

I am trying to write a simple application that can read msr registers, and am running this application from userspace. I have loaded the msr module and given read permissions for everyone to /dev/cpu/*/msr. But still the user is not able to access…
futureishere
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Executing rdmsr / wrmsr with secure boot on?

I'm trying to undervolt my CPU on a Intel Skylake machine running Ubuntu 18.04 / kernel 4.18.0-16 in Secure Boot mode and need to read/write MSR 0x150. I have signed and loaded the msr.ko kernel module, but can't run the executables rdmsr and wrmsr…
Bim
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Haswell microarchitecture don't have Stalled-cycles-backend in perf

I installed perf on Haswell CPU( Intel Core i7-4790 ). But the "perf list" does not include "stalled-cycles-frontend" nor "stalled-cycles-backend". I checked the…
hank wing
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Unable to disable Hardware prefetcher in Core i7

I am getting Error while trying to disable Hardware prefetcher in my Core i7 system. I am following the method as per the link How do I programmatically disable hardware prefetching? In my system grep -i msr /boot/config-$(uname…
bholanath
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Will memory write be visible after sending an IPI on x86?

I have read Intel 64 and IA-32 Architectures SDM vol 3A, 9.2 MEMORY ORDERING, but there was one question that kept bothering me. If I first write to a memory address, then send an interprocessor interrupt(IPI) with x2APIC, that mean sending IPI…
untitled
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How does Intel's RAPL estimate the power consumption

First of all, I do not know whether I should be asking this here or in the Electronics StackExchange, so please let me know if you think I should ask it there. I am interested in measuring the energy consumption of each CPU core in Intel CPUs. I…
Juan González
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CPUID: Why must MISC_ENABLE.LCMV be set to 0 for some functions? Can I temporarily overwrite it?

I'm trying to use CPUID, but there are some strings attached. According to sandpile.org's CPUID page, CPUID standard functions 0000_0004h and up will only work if the MISC_ENABLE.LCMV flag is set to 0. This flag is bit 22 of model-specific…
Mike S
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Setting root-only permissions on /dev files and build binary

As part of a build process, I want to run the following two commands: sudo chmod a+r /dev/cpu/*/msr sudo setcap cap_sys_rawio=ep ./bench This sets the /dev/cpu/*/msr files exposed by the msr kernel module to world-readable, and sets additional…
BeeOnRope
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x86 CPU Modes / Rings During Boot Process

I currently try to understand how exactly the platform initialization works on modern UEFI x86 systems. However, it is unclear how the privilege modes are defined and where and how they change. I recently saw a document from Intel that…
Benedict Schlüter
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Read PMU counters using wrmsrl and rdmsrl

I'm trying to read the LLC cache miss hardware counter in a Linux kernel module on an Intel Xeon gold (Skylake generation) processor. The result of the following code is always zero: #define PMC_ESEL_UMASK_SHIFT 8 #define PMC_ESEL_CMASK_SHIFT…
Mohammad Siavashi
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How to disable L3 cache prefetcher on Intel Xeon Scalable Processor?

I have searched Intel manual Vol.4. MSR 0x1a4 can control L1 cache prefetcher and L2 cache prefetcher, but I just want to disable L3 cache prefetcher. Which MSR can control it?
Jack
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Reading Current Uncore Frequency and Setting Uncore Frequency Multipliers

I'm working on a project that requires reading and setting Uncore Frequency on an Intel Skylake Xeon Gold 6126 Server CPU (I will need to do the same for another Haswell based processor). I'm running an Ubuntu with Linux 4.15.0-134. I've loaded the…
Tez_Nikka
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AMD Epyc (Zen 2) disable HW Prefetch L2

I wan to disable all hardware prefetching on an AMD Epyc 7702P (Zen 2 / Rome). I don't find anything related in the official tech docs (Processor Programming Reference 17H and Manuals). However, according to BKDG document for 15h. I have managed to…
ant
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