I am a Jr. Digital Design Engineer specializing in digital hardware description with VHDL. I am also an avid Python, computer vision and machine learning enthusiast and hope to come across opportunities to learn more on and integrate these subjects. I hope to help other people learn about VHDL while honing my own skill.

entity T01_Hello_Stack_Overflow is
end entity;

architecture sim of T01_Hello_Stack_Overflow is
begin

    process is
    begin

        report "Hello Stack Overflow!";
        wait;

    end process;

end architecture;