I work for SynthWorks, a VHDL training company. If you are looking to improve your VHDL verification process, check out our VHDL Testbenches and Verification class at: http://www.synthworks.com/vhdl_testbench_verification.htm

I am also the co-founder and chief architect of the Open Source VHDL Verification Methodology (OSVVM). OSVVM is a Free, Open Source VHDL Verification Methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a simple, readable, and powerful testbench that has similar capabilities to other verification languages (such as SystemVerilog + UVM) and is suitable for either a simple FPGA block or a complex ASIC. See: https://osvvm.github.io/ and http://osvvm.org/. We teach OSVVM in our classes.

I am also the IEEE VHDL working group chair. If you wish to submit an idea or issue, please see: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues. If you are answering VHDL questions here, please consider joining the VHDL Working Group. See our working group page at: https://ieee-p1076.gitlab.io/. We do our work using Web Meetings, GitLab issues (and older stuff TWIKI), gitter.im, and email (older way). Drop me an email (see below) and I will help you get set up.

email: jim at synthworks dot com