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jbdavid
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  • San Jose, CA
  • Member since September 14 2008
  • 118 profile views
  • Last seen Jul 20 '13 at 01:04

Mixed Signal Design Verification languages: -Verilog (in all its flavors esp Verilog-AMS) -perl -SKILL (the cadence variant of LISP) -(someday) Python & Matlab