Deficit Round Robin (DRR), also Deficit Weighted Round Robin (DWRR), is a scheduling algorithm for the network scheduler. DRR is, like weighted fair queuing (WFQ), a packet-based implementation of the ideal Generalized Processor Sharing (GPS) policy. It was proposed by M. Shreedhar and G. Varghese in 1995 as an efficient (with O(1) complexity) and fair algorithm.[1]

Details

In DRR, a scheduler handling N flows[lower-alpha 1] is configured with one quantum for each flow. This global idea is that, at each round, the flow can send at most bytes, and the remaining, if any, is reported to the next round. In this way, the minimum rate that flow will achieve over a long term is ; where is the link rate.

Algorithm

The DRR scans all non-empty queues in sequence. When a non-empty queue is selected, its deficit counter is incremented by its quantum value. Then, the value of the deficit counter is a maximal number of bytes that can be sent at this turn: if the deficit counter is greater than the packet's size at the head of the queue (HoQ), this packet can be sent, and the value of the counter is decremented by the packet size. Then, the size of the next packet is compared to the counter value, etc. Once the queue is empty or the value of the counter is insufficient, the scheduler will skip to the next queue. If the queue is empty, the value of the deficit counter is reset to 0.

Variables and Constants
    const integer N             // Nb of queues
    const integer Q[1..N]       // Per queue quantum 
    integer DC[1..N]            // Per queue deficit counter
    queue queue[1..N]           // The queues
Scheduling Loop
while true do
    for i in 1..N do
        if not queue[i].empty() then
            DC[i]:= DC[i] + Q[i]
            while( not queue[i].empty() and
                         DC[i] ≥ queue[i].head().size() ) do
                DC[i] := DC[i] − queue[i].head().size()
                send( queue[i].head() )
                queue[i].dequeue()
            end while 
            if queue[i].empty() then
                DC[i] := 0
            end if
        end if
    end for
end while

Performances: fairness, complexity, and latency

Like other GPS-like scheduling algorithm, the choice of the weights is left to the network administrator.

Like WFQ, DRR offers a minimal rate to each flow whatever the size of the packets is. In weighted round robin scheduling, the fraction of bandwidth used depend on the packet's sizes.

Compared with WFQ scheduler that has complexity of O(log(n)) (n is the number of active flows/queues), the complexity of DRR is O(1), if the quantum is larger than the maximum packet size of this flow. Nevertheless, this efficiency has a cost: the latency, i.e., the distance to the ideal GPS, is larger in DRR than in WFQ.[2] More on the worst-case latencies can be found here.[3]

Implementations

An implementation of the deficit round robin algorithm was written by Patrick McHardy for the Linux kernel[4] and published under the GNU General Public License.

In Cisco and Juniper routers, modified versions of DRR are implemented: since the latency of DRR can be larger for some class of traffic, these modified versions give higher priority to some queues, whereas the others are served with the standard DRR algorithm.[5][6]

See also

Notes

  1. Flows may also be called queues, classes or sessions

References

  1. Shreedhar, M.; Varghese,G. (October 1995). "Efficient fair queueing using deficit round robin". ACM SIGCOMM Computer Communication Review. 25 (4): 231. doi:10.1145/217391.217453. ISSN 0146-4833.
  2. Lenzini, L.; Mingozzi, E.; Stea, G. (2002). "Aliquem: A novel DRR implementation to achieve better latency and fairness at O(1) complexity". IEEE 2002 Tenth IEEE International Workshop on Quality of Service (Cat. No.02EX564). pp. 77–86. doi:10.1109/IWQoS.2002.1006576. ISBN 978-0-7803-7426-3. S2CID 62158653.
  3. Tabatabaee, Seyed Mohammadhossein; Le Boudec, Jean-Yves (May 2021). "Deficit Round-Robin: A Second Network Calculus Analysis". 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS) (PDF). Nashville, TN, USA: IEEE. pp. 171–183. doi:10.1109/RTAS52030.2021.00022. ISBN 978-1-6654-0386-3. S2CID 235294011.
  4. "DRR Linux kernel network scheduler module". kernel.org. Retrieved 2013-09-07.
  5. Lenzini, Luciano; Mingozzi, Enzo; Stea, Giovanni (2007). "Performance Analysis of Modified Deficit Round Robin Schedulers". IOS Journal of High Speed Networks. 16 (4): 399–422.
  6. Lenzini, Luciano; Mingozzi, Enzo; Stea, Giovanni (2006). Performance Analysis of Modified Deficit Round Robin Schedulers (Technical report). Dipartimento di Ingegneria della Informazione, University of Pisa.
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