0

I am trying to get partial sums of 18*18 multiplication. I want to save these in a multidimensional array(18*36) where each index of array contains a partial sum. i tried using an array of std_logic_vector. But I got no results. I even tried array of bit_vector and also also of bits. Here is my VHDL code.

entity partial is
port(
   A : in bit_vector(17 downto 0);
   B : in bit_vector(17 downto 0);
   C : out bit_vector(35 downto 0);
   D : out bit
);
end partial;

architecture Behavioral of partial is
   type partial_sums is array (17 downto 0, 35 downto 0) of bit;
   signal sums : partial_sums;

begin

   process (A,B)
   begin

    --sums <= (others=> (others=>'0'));

    --for j in 0 to 17 loop
    --   sums(j)<="000000000000000000000000000000000000";
    --end loop;

      for i in B'low to B'high loop
         if ( B(i)='1') then
            for p in A'low to A'high loop
               sums(i,p) <= A(p);   
            end loop;
         end if;
      end loop;

      D <= sums(0,0);

   end process;
end Behavioral;

I am always getting 0 in D no matter what indices use in sums array. Please help me.

em.eh.kay
  • 350
  • 1
  • 7
skjindal93
  • 706
  • 1
  • 16
  • 34
  • How are you testing it? It might be worth posting a simple testbench. –  Jan 16 '13 at 16:56
  • I am using Xilinx for it. Here is the test bench of the vhdl file i created. http://pastebin.com/raw.php?i=HCRTUZ9b – skjindal93 Jan 16 '13 at 17:18

3 Answers3

2

You are assigning sums to D in a combinatorial process, but sums is not in the process sensitivity list.

Probably the best way to go here is to move the assignment of D outside of the process.

zennehoy
  • 6,405
  • 28
  • 55
  • Nice catch. Wondering why the user uses bit instead of std_logic, though. – FRob Jan 16 '13 at 17:39
  • 1
    Bit is simpler, should be faster to simulate. It's better to wonder why it isn't used more often when we don't need to model unknowns and resolved types. –  Jan 16 '13 at 17:41
  • @FRob: Probably because some professor doesn't want to explain 'X', 'Z', etc. – zennehoy Jan 16 '13 at 17:41
0

A word of warning: Xilinx ISE including verison 14 has problems with multidimensional arrays and vector assignments. You cannot use three-dimensional arrays and you cannot use unconstrained arrays of arrays. Also, using multidimensional arrays, assignment is somewhat flaky at best. When I used ISE last, it often would complain about legal assignments not having the desired width even when ModelSim would compile and simulate fine.

Your actual problem is likely that you only assign the lower 18 bits of each entry in sums, where the entry is actually 36 bits wide.

For better readability you should probably define

type partial_sums is array (natural range <>) of bit_vector(35 downto 0);

and then use direct bit_vector assignments without loops. Your fixed values in D are likely due to either B having no bits set to '1' (where you should get U because you lack a default value) or because A's bits are always '0', where you should get all '0' in the lower 18 bits and all 'U' in the upper 18 bis.

EDIT: However, bit is resolved logic, so you will only see '0' or '1' in there. IMO you should use std_logic.

FRob
  • 3,883
  • 2
  • 27
  • 40
  • Earlier I tried all these things, but got unexpected results. The solution that sums is not in the sensitivity list solved my problem.Thanks – skjindal93 Jan 16 '13 at 18:10
0

Actually, it works fine, loading appropriate test data into the partial product array.

You just aren't waking the process up again to collect the result on D. Add "sums" to the sensitivity list of process "partial" to do so.

Or better, make it a clocked process (as you will have to, to get any sensible results when you get to synthesis).

See this Q/A on how signal assignments work. Is process in VHDL reentrant?

Community
  • 1
  • 1