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Questions tagged [vhdl]

VHDL (VHSIC Hardware Description Language) is a language used in electronic design to describe digital systems such as FPGA (field-programmable gate arrays) and IC (integrated circuits).

A hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays (FPGAs) and integrated circuits (ICs). VHDL can also be used as a general-purpose parallel programming language

When asking a question, please specify whether you are looking for a synthesizable solution or one for a testbench.

The Wikipedia page says:

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.

VHDL is standardized as IEEE 1076-2008 (non-free download).

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What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)

What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more common software development fields?
JeffV
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clk'event vs rising_edge()

I had always used this for detecting a rising edge: if (clk'event and clk='1') then but this can also be used: if rising_edge(clk) then Reading this post, rising_edge(clk) is recommended, but there is also a comment indicating that rising_edge(clk)…
Diego Herranz
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VHDL - How should I create a clock in a testbench?

How should I create a clock in a testbench? I already have found one answer, however others on stack overflow have suggested that there are alternative or better ways of achieving this: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_tb IS…
alexdavey
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Multiple assignments to the same register in an RTL block with Kansas Lava

I'm having trouble understanding Kansas Lava's behaviour when an RTL block contains multiple assignments to the same register. Here's version number 1: foo :: (Clock c) => Signal clk Bool foo = runRTL $ do r <- newReg True r := low …
Cactus
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VHDL Variable Vs. Signal

I have been reading a text (Don't have it in front so can't give the title) about VHDL programming. One problem I've been having a hard time understanding from the text is when to use a variable vs a signal. I think I have a clear understanding of…
doddy
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vsim does not accept -modelsimini parameter on Windows

I'm using the command line argument -modelsimini to specify my own modelsim.ini file for most QuestaSim / ModelSim executables. This works perfectly fine on Linux for vcom and vsim, as well as for vcom on Windows. But the Windows vsim…
Paebbels
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Best way to learn VHDL?

I want to learn VHDL but I really don't know from where to start. I want some advice and explanation about the software I need to get started. I would like also to get some references in order to learn it efficiently without wasting time by…
Black
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Professional VHDL IDE?

Is there a good IDE to work with VHDL projects ? Or are most of the professionals working with emacs/vim/notepad++ ?
Aurelien Ribon
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Experiences with Test Driven Development (TDD) for logic (chip) design in Verilog or VHDL

I have looked on the web and the discussions/examples appear to be for traditional software development. Since Verilog and VHDL (used for chip design, e.g. FPGAs and ASICs) are similar to software development C and C++ it would appear to make…
Brian Carlton
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VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC?
prosseek
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How to "slice" an std_logic_vector in VHDL?

I'm developing a little thing in VHDL and am quite new to it. I'm having trouble figuring out how to slice a bigger std_logic_vector into a smaller one. For instance I have 3 signals: signal allparts: std_logic_vector(15 downto 0); signal…
Earlz
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VHDL Case/When: multiple cases, single clause

Inside a process I have something like this: CASE res IS WHEN "00" => Y <= A; WHEN "01" => Y <= A; WHEN "10" => Y <= B; WHEN "11" => Y <= C; WHEN OTHERS => Y <= 'X'; END CASE; Note that case "00" and "01" get the same value. Is there a…
Jay Wick
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shift a std_logic_vector of n bit to right or left

I have a vector signal tmp : std_logic_vector(15 downto 0) I have to shift it to left or right of n bit. how can I realize this operation. I thought to concatenation operation but I didn't know how use it.
Mazzy
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When must a signal be inserted into the sensitivity list of a process

I am confused about when a signal declared in an architecture must be inserted into the sensitivity list of a process. Is there is a general law that can be followed in any situation? I have real difficulties understanding when I have to include a…
Mazzy
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Error adding std_logic_vectors

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity add_module is …
Mike21
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