Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions
58
votes
15 answers

CUDA or FPGA for special purpose 3D graphics computations?

I am developing a product with heavy 3D graphics computations, to a large extent closest point and range searches. Some hardware optimization would be useful. While I know little about this, my boss (who has no software experience) advocates FPGA…
Fredriku73
  • 3,170
  • 4
  • 35
  • 32
31
votes
6 answers

Open-source field-programmable gate array (FPGA) development tools

I want to pick up FPGA programming. I've heard all types of horror stories of proprietary tools. Is there any entirely open-source tool chain available? If not, how should I learn this? My background: familiar with Scheme, C++, assembly, and MIPS…
anon
  • 41,035
  • 53
  • 197
  • 293
31
votes
8 answers

Experiences with Test Driven Development (TDD) for logic (chip) design in Verilog or VHDL

I have looked on the web and the discussions/examples appear to be for traditional software development. Since Verilog and VHDL (used for chip design, e.g. FPGAs and ASICs) are similar to software development C and C++ it would appear to make…
Brian Carlton
  • 7,545
  • 5
  • 38
  • 47
30
votes
9 answers

Can you program FPGAs in C-like languages?

At university I programmed a FPGA in a C-like language. However, I also know that one usually programs FPGAs in Verilog or VHDL. Is this a designer choice? If so, what are the performance drawbacks? I would ideally like to program the FPGA in a…
intrigued_66
  • 16,082
  • 51
  • 118
  • 189
30
votes
6 answers

C-to-hardware compiler (HLL synthesis)

I try to make an survey/history of all C-to-hardware compilers. For all that dont know them: they take C code then translate it into some hardware description language (like VHDL or Verilog), which then can be used to generate hardware (usually it…
flolo
  • 15,148
  • 4
  • 32
  • 57
28
votes
8 answers

Neural Network simulator in FPGA?

To learn FPGA programming, I plan to code up a simple Neural Network in FPGA (since it's massively parallel; it's one of the few things where an FPGA implementation might have a chance of being faster than a CPU implementation). Though I'm familiar…
anon
  • 41,035
  • 53
  • 197
  • 293
27
votes
4 answers

Algorithms FPGAs dominate CPUs on

For most of my life, I've programmed CPUs; and although for most algorithms, the big-Oh running time remains the same on CPUs / FPGAs, the constants are quite different (for example, lots of CPU power is wasted shuffling data around; whereas for…
anon
  • 41,035
  • 53
  • 197
  • 293
26
votes
3 answers

How can the linux kernel be forced to enumerate the PCI-e bus?

Linux kernel 2.6 I've got an fpga that is loaded over GPIO connected to a development board running linux. The fpga will transmit and receive data over the pci-express bus. However, this is enumerated at boot and as such, no link is discovered…
reign_man
  • 569
  • 2
  • 8
  • 21
23
votes
7 answers

What are some practical applications of an FPGA?

I'm super excited about my program powering a little seven-segment display, but when I show it off to people not in the field, they always say "well what can you do with it?" I'm never able to give them a concise answer. Can anyone help me out?
Willem Ellis
  • 4,886
  • 7
  • 38
  • 55
22
votes
5 answers

Error adding std_logic_vectors

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity add_module is …
Mike21
  • 221
  • 1
  • 2
  • 3
21
votes
10 answers

What FPGAs (Field-Programmable Gate Arrays) can one buy to experiment with at home?

What is an FPGA, and where can I buy one? How much do they cost? What sort of system do you need to experiment with them? How to program them? Can you "load" if that's the right term an FPGA using an ordinary Mac? Are they extremely expensive or can…
Fattie
  • 27,874
  • 70
  • 431
  • 719
15
votes
1 answer

Relation between LUTs, logic cell, logic elements, system gates

My question is related to difference and relationship between these terminology: LUTs Logic Cell Logic Elements(LE) System Gates I know that a lot depends on FPGA producer, but for example an FPGA vendor that state of one of it's products this:…
Yaro
  • 475
  • 2
  • 6
  • 16
15
votes
1 answer

3-stage MD5 pipeline in VHDL

I am trying to implement a 3-stage MD5 pipeline according to this link. In particular the algoritms on page 31. There is also another document which describes data forwarding. The MD5 algoritm is described in RFC1321. This is done in an FPGA…
jgr
  • 3,914
  • 2
  • 24
  • 28
14
votes
2 answers

Where can I find a definitive list of the ModelSim error codes?

I am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice range direction "downto" specified in slice with prefix of unknown direction. This is just an example message; I understand what it…
Philippe
  • 3,700
  • 1
  • 21
  • 34
14
votes
4 answers

What does "others=>'0'" mean in an assignment statement?

cmd_register: process (rst_n, clk) begin if (rst_n='0') then cmd_r<= (others=>'0'); elsif (clk'event and clk='1') then cmd_r<=...; end if; end process cmd_register; I know "<=" specifies assignment but what is others? And what does…
1
2 3
99 100