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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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vsim does not accept -modelsimini parameter on Windows

I'm using the command line argument -modelsimini to specify my own modelsim.ini file for most QuestaSim / ModelSim executables. This works perfectly fine on Linux for vcom and vsim, as well as for vcom on Windows. But the Windows vsim…
Paebbels
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What is the difference between Verilog ! and ~?

So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like: if(~x && ~y) begin //do stuff end i.e. If x is NOT ONE and y is NOT ONE…
SleepingSpider
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The font of my modelsim is too small to see

As you can see, the font of modelsim's text editor is very small. But I can't change the size in Tools->Edit Preferences->Source Window->Fonts. However, I can make the letters bigger by set the DPI higher(through System Settings->Fonts) or set the…
Wtswkz
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How does signal assignment work in a process?

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here: ... signal x,y,z : bit; ... process (y) begin x<=y; z<=not x; end process; The example says this: If the signal…
Andry
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Where can I find a definitive list of the ModelSim error codes?

I am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice range direction "downto" specified in slice with prefix of unknown direction. This is just an example message; I understand what it…
Philippe
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Wait until =1 never true in VHDL simulation

Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? The console output is simply GOT HERE. It never gets to the line GOT HERE 2. I would think that having the same wait until = 1 twice…
Russell
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Is there a way to toggle leaf names in ModelSim through the TCL API?

I am looking for a way to toggle leaf names of the nets in ModelSim view, in GUI mode. In other words, an equivalent of pressing "Toggle leaf names <-> full names" button: I am aware of the way of adding short names. For example, I've been using…
user405725
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How to open Modelsim project files

I can open Modelsim project files by doing File->Recent Projects. However I do not know any other way to open projects. If I use File->Open it only opens up individual files, not projects. How can projects be opened?
neuromancer
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Altera Quartus falsly says Modelsim isn't installed

Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it, fire up the simulation window and configure the in…
Johan
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ModelSim-Altera error

I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch screen by terasic with the Cyclone IV EP4CE115 by…
Doron Behar
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Configure ModelSim simulation to display text

Can I make ModelSim simulation to display text (rather than a numeric value) on a signal? I have a couple of state-machine states say, localparam S_IDLE = 2'b00; localparam S_START = 2'b01; localparam S_STOP = 2'b10; Is there a way to display…
SleepingSpider
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Detect timescale in System Verilog

How do I detect the timescale precision used in a simulation from the source code ?. Consider I have a configuration parameter(cfg_delay_i) of some delay value given by user in timeunits as fs .If the user gives 1000 , my code has to wait 1000fs or…
Sreejin TJ
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Quartus II use file only in simulation

I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My…
alabamajack
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VHDL test results into jUnit (or other Jenkins-recognized) format

I'm setting up automated regression testing for an FPGA project, almost exactly as described here: Continuous integration of complex reconfigurable systems Now I want to get test results (from VHDL REPORT statements in ModelSim simulation) to…
Ben Voigt
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VCD dump for vhdl simulation via modelsim. HOWTO?

It's the first time i try to generate a VCD and i am getting some troubles. I have a testbench called bench_minimips.vhdl that contain the entity sim_minimips. I want simulate it and get a VCD out of it. i am typing the following command in the…
Stefano
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