Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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4 answers

How can I use foreach and fork together to do something in parallel?

This question is not UVM specific but the example that I am working on is UVM related. I have an array of agents in my UVM environment and I would like to launch a sequence on all of them in parallel. If I do the below: foreach (env.agt[i]) begin …

asked Nov 05 '13 at 15:45

Kaushal Modi

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2 answers

Best way to access the uvm_config_db from the testbench?

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was…

verilog system-verilog uvm

asked Nov 07 '13 at 15:59

nguthrie

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2 answers

Detect timescale in System Verilog

How do I detect the timescale precision used in a simulation from the source code ?. Consider I have a configuration parameter(cfg_delay_i) of some delay value given by user in timeunits as fs .If the user gives 1000 , my code has to wait 1000fs or…

system-verilog modelsim uvm system-verilog-dpi

asked Oct 01 '19 at 04:42

Sreejin TJ

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2 answers

Difference Between the uvm_analysis ports

Can you please help to understand the functionality and clear difference between: uvm_analysis_export uvm_analysis_port uvm_analysis_imp I have searched in internet, there are some explanations, like…

uvm

asked Mar 01 '16 at 05:23

haykp

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2 answers

uvm_event and system verilog event difference

What is the advantage of uvm_event over the SystemVerilog event ? Can someone explain with small pseudo code ?

system-verilog uvm

asked Sep 07 '16 at 02:56

Ashutosh Rawal

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2 answers

UVM blocking assignment race conditions

I have a doubt about race conditions in SystemVerilog, especially in UVM. In the standard case what we have is multiple drivers that drive our dut in the same front of the clock, generating some function calls in the scoreboard. These calls are…

system-verilog uvm

asked Nov 14 '14 at 22:45

arandomuser

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1 answer

Restricting access to virtual interface signals in classes

I'd like to know if it's possible to somehow figure out if, by mistake, inside a UVM driver the developer writes to a DUT output signal, instead of an input signal. I've tried this out and there is no compile/runtime error message. The example is…

system-verilog uvm

asked Feb 25 '14 at 17:30

Tudor Timi

7,453
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4 answers

UVM RAL: Randomizing registers in a register model

I have a large register map modelled with RAL and I would like to randomize some of the registers. If I want to constrain the registers seperately then this is simple: reg_model.register_a.randomize() with {value >…

system-verilog uvm

asked Jan 10 '14 at 20:43

nguthrie

2,615
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26
43

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2 answers

Piggybacking to UVM error

Is there an easy way to piggy back a custom function to UVM_ERROR macro without manipulating the UVM library ?(i.e whenever a UVM error is invoked anywhere in the environment I want my function to be called along with it.)

verilog system-verilog uvm

asked Sep 25 '13 at 19:15

Jean

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1 answer

Factory overriding parameterized class in UVM

I have a parameterized seq_item as below class seq_item#(int A = 64) extends uvm_sequence_item; `uvm_object_param_utils(seq_item#(A)) rand logic [A-1:0] v; constraint v_c { v inside {[0:1000]}; } endclass : seq_item class…

system-verilog uvm

asked Feb 14 '20 at 12:19

user1978273

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3 answers

How to bind a SV interface signal to a VHDL type?

I am trying to bind an interface to my VHDL module. The signal that I want to bind to is defined as follows in the module: TYPE dut_fsm_type is ( IDLE_STATE, WAIT_STATE, …

vhdl system-verilog uvm questasim

asked Nov 23 '16 at 23:23

noobuntu

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1 answer

Implementing UVM Agent in slave mode

I have a slave model implemented in uvm_agent. By "slave" I meant that it can not initiate transaction by itself. Transaction is always initiated by the other side (master DUT). So it is kind of passive agent (although it is still able to transmit…

system-verilog uvm

asked Feb 11 '15 at 06:36

AldoT

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2 answers

Passing "type" argument to functions

Is it possible to pass a type argument to function so that create_eclass* function can only be written once by passing class type argument to it ? class bclass; virtual function void print(); $display("Base Class"); endfunction endclass class…

oop verilog system-verilog uvm

asked Feb 04 '15 at 23:02

Jean

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119

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4 answers

UVM shared variables

I have a doubt regarding UVM. Let's think I have a DUT with two interfaces, each one with its agent, generating transactions with the same clock. These transactions are handled with analysis imports (and write functions) on the scoreboard. My…

system-verilog uvm

asked Oct 19 '14 at 11:01

arandomuser

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3 answers

Get system time in VCS

Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time). Is there way to print system time for every uvm_info printed ?

verilog system-verilog uvm synopsys-vcs

asked Sep 25 '14 at 19:23

Jean

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