Questions tagged [synopsys-vcs]

Synopsys VCS Verilog Simulator

Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, VCS (Verilog Compiled code Simulator) was purchased by Synopsys, where development continued. Due to a strategic decision to support SystemVerilog (instead of SystemC), and the acquisition of Superlog (the forerunner to SystemVerilog), Synopsys/VCS was the first SystemVerilog simulator in the market. Supports simulation of designs written in VHDL as well.

47 questions

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4 answers

SystemVerilog: How to connect C function using DPI call in VCS simulator?

I have the following files: C file with functions: // funcs.c #include void something() { printf("something\n"); sayHello(); } System verilog file: // hello_world.v module kuku; export "DPI-C" function sayHello; import…

c system-verilog synopsys-vcs system-verilog-dpi

asked Nov 11 '14 at 09:21

SomethingSomething

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3 answers

Get system time in VCS

Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time). Is there way to print system time for every uvm_info printed ?

verilog system-verilog uvm synopsys-vcs

asked Sep 25 '14 at 19:23

Jean

21,665
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119

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0 answers

Can VCS output a shared library instead of an executable (simv)?

We've a C++ application intended to be run on a x86 hosted RISC-V processor. The application is executed on both the host (x86) and the tethered RISC-V processor. The RISC-V processor is emulated on an FPGA. We have a shared library called…

shared-libraries fpga system-verilog riscv synopsys-vcs

asked Mar 02 '20 at 03:54

vb000

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2 answers

Connect different port width

Suppose my module has a 8-bit input and 8-bit output module MyModule (input logic [7:0] in, output logic [7:0] out); ... endmodule : MyModule If I want to connect a 1-bit input in and leave the other bits as zero, the following works: MyModule…

system-verilog synopsys-vcs

asked Feb 11 '19 at 09:54

qwr

9,525
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1 answer

Synopsys VCS Warning for `define redefined

Is it possible to generate a warning or error in Synopsys VCS compiler if a `define macro is redefined? `define DATWIDTH_SZ `DAT_SZ `define DATWIDTH_SZ 512

verilog synopsys-vcs

asked Feb 06 '14 at 18:57

Jean

21,665
24
69
119

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2 answers

Using nested vcs +incdir+

I have a situation where I need to package a SystemVerilog environment and export it to a customer. I need to make sure I provide as few +incdir+ as possible for the customer to compile. The environment is huge, and it contains many IPs and hence…

verilog system-verilog synopsys-vcs

asked Feb 22 '23 at 04:25

user1978273

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1 answer

TCL processing arguments template, why [set argv {}]

Following is a template from tcl wiki link, this code can be used to process tcl command-line arguments. I wonder why we need [set argv {}] at line 7. # If this script was executed, and not just "source"'d, handle argv if {[info exists argv0] && [ …

bash shell tcl vivado synopsys-vcs

asked Dec 08 '21 at 07:48

Phantom

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1 answer

System Verilog: clocking block effects propagation

Consider the following SV code snippet: module clocks(); logic a ; bit clk =0; initial begin forever #1ns clk = ~clk ; end clocking cb@(posedge clk); default input #1step output negedge; output a; endclocking …

verilog system-verilog hdl questasim synopsys-vcs

asked Mar 24 '21 at 16:58

atadocca

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1 answer

How to use Find Scope in Synopsys Verdi

The "Find Scope..." option in Synopsys Verdi doesn't seem to be able to find anything other than top level modules. I have the Scope Type set to Module and I have tried a bunch of different variations: 1) the module name with the * wildcard before…

verilog synopsys-vcs

asked May 21 '20 at 17:01

Brian R

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1 answer

How to properly declare an N-dimensional queue inline in SystemVerilog?

If I have 2D queue of ints, I would expect to be able to declare it inline like so: int my_queue[$][$] = {{1, 2}, {3, 4}}; I have also seen typedef int int_queue[$]; int_queue my_queue[$] = {{1, 2}, {3, 4}}; Instead, when I compile, VCS provides…

system-verilog synopsys-vcs

asked Feb 15 '20 at 19:46

Sean McLoughlin

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1 answer

Why always block not reactivating when there is a reassignment of logic described in sensitivity list

Signal driver_a is reassigned in the always block back to 0, but why is the always block not activating and assign value to driver_b ? always @(driver_a) begin driver_b = driver_a; driver_a = 0; end initial begin driver_a = 0; driver_b = 0; #2…

verilog system-verilog hdl synopsys-vcs

asked Feb 09 '19 at 04:27

TheSprintingEngineer

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1 answer

Does Synopsys VCS gives test names that hit the cover?

Here's the flow of the problem. I wrote some general cover. There are many tests that may hit a particular cover. Some test will not hit it. VCS functional coverage report gives combined hits for a particular cover. I want to see what tests hit…

system-verilog test-coverage synopsys-vcs

asked Aug 16 '17 at 22:45

Prateek Prasad

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2 answers

make a list into a collection in TCL

I want to create a collection from a list. friends1 is a list of names. I am trying to do: set friends2 "" foreach frnd $friends1 { append_to_collection friends2 $frnd } Error: At least one collection required for…

collections tcl synopsys-vcs

asked Jul 02 '16 at 12:26

Tlalit

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1 answer

Double colon :: in Tcl

In some EDA tool's Tcl script (i.e Cadence Enounter), what does the double :: do? report::TimeStamp PrePlace "START PrePlace"

tcl cadence synopsys-vcs

asked Oct 30 '15 at 16:53

Bryan

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1 answer

why I am not allowed to define unpacked array variable by 8'CC in system verilog?

I have tried with the below code: module try; int a[8]; initial begin a = 8'hCC; $display(a); end endmodule This is giving error as: Incompatible complex type assignment Type of source expression is incompatible with type of target expression. …

verilog system-verilog synopsys-vcs

asked Sep 16 '14 at 12:00

Megha Brahmbhatt

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