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We've a C++ application intended to be run on a x86 hosted RISC-V processor. The application is executed on both the host (x86) and the tethered RISC-V processor. The RISC-V processor is emulated on an FPGA. We have a shared library called libfpga_intf.so consisting of drivers providing a C API to the RISC-V processor on the FPGA.

We also wish to simulate the RISC-V processor on VCS, as access to FPGA system is limited. I've systemverilog models of the RISC-V processor and the FPGA interface which I'd like to compile with the C++ application. Is there a way I could compile the SV models with VCS to generate libfpga_intf.so equivalent.

(I could use SV DPI to compile application into VCS simv, which means the application executable is simv and command line interface is very different to what is actually intended by the application. I prefer the software interface to be a drop in replacement to the real FPGA system.)

vb000
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    There used to be a `slave` simulation mode in vcs-mx which was used in similar applications. There is no description of it in documentation. Check with https://solvnet.synopsys.com/ or ask synopsys directly. – Serge Mar 02 '20 at 11:42
  • Thanks @Serge! That seems like the one I'm looking for.. I'll try it out! – vb000 Mar 02 '20 at 18:31

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