Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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5 answers

Using wire or reg with input or output

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

verilog system-verilog

asked Mar 19 '11 at 06:10

node ninja

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2 answers

What do curly braces mean in Verilog?

I am having a hard time understanding the following syntax in Verilog: input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result = {{16{a[15]}}, {a[15:0]}}; I know the assign statement will wire something up to the…

concatenation verilog system-verilog

asked Jan 20 '10 at 15:59

Alex. H

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4 answers

What is the difference between == and === in Verilog?

What is the difference between: if (dataoutput[7:0] == 8'bx) begin and if (dataoutput[7:0] === 8'bx) begin After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

verilog system-verilog hdl

asked May 08 '11 at 13:07

user478571

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3 answers

How to declare and use 1D and 2D byte arrays in Verilog?

How to declare and use 1D and 2D byte arrays in Verilog? eg. how to do something like byte a_2D[3][3]; byte a_1D[3]; // using 1D for (int i=0; i< 3; i++) { a_1D[i] = (byte)i; } // using 2D for (int i=0; i< 3; i++) { for (int j=0; j< 3;…

arrays byte verilog system-verilog

asked Jun 10 '10 at 03:46

Ursa Major

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1 answer

Difference among always_ff, always_comb, always_latch and always

I am totally confused among these 4 terms: always_ff, always_comb, always_latch and always. How and for what purpose can these be used?

system-verilog

asked Apr 16 '14 at 06:30

user2138826

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2 answers

Indexing vectors and arrays with +:

I am seeing a code in SystemVerilog which has something like this: if(address[2*pointer+:2]) do_something; How should I understand the +: when indexing this vector? I found that it is called bit slicing, but I can't find an explanation about it.

system-verilog

asked Aug 05 '13 at 20:56

DOS

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7 answers

packed vs unpacked vectors in system verilog

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this: node [range_hi:range_lo]x; and others that are defined like this: node y[range_hi:range_lo]; I understand that x is defined as packed, while y is…

vector system-verilog

asked Jan 25 '09 at 12:35

Nathan Fellman

122,701
101
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6 answers

How to interpret blocking vs non blocking assignments in Verilog?

I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram. Do we have to infer that a non blocking assignment gives us a register? Then according to this statement c <= a+b , c…

verilog system-verilog

asked Jan 11 '11 at 01:19

infinitloop

2,863
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8 answers

VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC?

vhdl verilog system-verilog systemc

asked Jun 30 '10 at 19:03

prosseek

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3 answers

What is `+:` and `-:`?

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example: logic [15:0] down_vect; logic [0:15] up_vect; down_vect[lsb_base_expr +: width_expr] up_vect [msb_base_expr +: width_expr] down_vect[msb_base_expr…

verilog system-verilog

asked Jul 22 '13 at 00:36

e19293001

2,783
9
42
54

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2 answers

ADDRESS WIDTH from RAM DEPTH

I am implementing a configurable DPRAM where RAM DEPTH is the parameter. How to determine ADDRESS WIDTH from RAM DEPTH? I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH) i.e ADDRESS WIDTH = log (base 2) RAM DEPTH. How to implement the log (base 2)…

verilog system-verilog

asked Mar 11 '11 at 06:20

Ashwini

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7 answers

Difference of SystemVerilog data types (reg, logic, bit)

There are different data types in SystemVerilog that can be used like the following: reg [31:0] data; logic [31:0] data; bit [31:0] data; How do the three of them differ?

system-verilog

asked Nov 08 '12 at 03:42

e19293001

2,783
9
42
54

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2 answers

What is the difference between = and <= in Verilog?

What is the difference between = and <= in this code? Also, how do I print the value of data? module always_example(); reg clk,reset,enable,q_in,data; always @ (posedge clk) if (reset) begin data <= 0; end else if (enable) begin data…

verilog system-verilog

asked Feb 16 '16 at 14:40

Hayder Al-Amily

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2 answers

How to define and initialize a vector containing only ones in Verilog?

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct? wire [127:0] mywire; assign mywire = 128'b1; assign mywire = {128{1'b1}}; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

verilog system-verilog register-transfer-level

asked Sep 30 '13 at 23:12

Veridian

3,531
12
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3 answers

Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0]…

verilog system-verilog

asked Nov 19 '13 at 08:44

Morgan

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