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Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

From Wikipedia:

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

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What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)

What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more common software development fields?
JeffV
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What is the difference between reg and wire in a verilog module?

When are we supposed to use reg and when are we supposed to use wire in a verilog module? I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of…
RaviTej310
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Using wire or reg with input or output

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?
node ninja
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What do curly braces mean in Verilog?

I am having a hard time understanding the following syntax in Verilog: input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result = {{16{a[15]}}, {a[15:0]}}; I know the assign statement will wire something up to the…
Alex. H
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What is the difference between == and === in Verilog?

What is the difference between: if (dataoutput[7:0] == 8'bx) begin and if (dataoutput[7:0] === 8'bx) begin After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)
user478571
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How to declare and use 1D and 2D byte arrays in Verilog?

How to declare and use 1D and 2D byte arrays in Verilog? eg. how to do something like byte a_2D[3][3]; byte a_1D[3]; // using 1D for (int i=0; i< 3; i++) { a_1D[i] = (byte)i; } // using 2D for (int i=0; i< 3; i++) { for (int j=0; j< 3;…
Ursa Major
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Difference between "parameter" and "localparam"

I'm writing a project with Verilog and want to use parameter to define some parameter in my module. But when I read in some source code, localparam sometimes is used instead of parameter. What's difference between them?
Micheal XIV
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What's the difference between $stop and $finish in Verilog?

I'm using a GUI simulator, and they both seem to do the same thing.
Steven
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Tool for drawing timing diagrams

Recently I am working with a hardware design group developing an ASIC. And I am drawing a lot of timing diagrams for which I am using Microsoft Excel, as it is easy to import into Word document. But, things are getting more and more difficult with…
Alphaneo
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Experiences with Test Driven Development (TDD) for logic (chip) design in Verilog or VHDL

I have looked on the web and the discussions/examples appear to be for traditional software development. Since Verilog and VHDL (used for chip design, e.g. FPGAs and ASICs) are similar to software development C and C++ it would appear to make…
Brian Carlton
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How to interpret blocking vs non blocking assignments in Verilog?

I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram. Do we have to infer that a non blocking assignment gives us a register? Then according to this statement c <= a+b , c…
infinitloop
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VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC?
prosseek
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What is `+:` and `-:`?

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example: logic [15:0] down_vect; logic [0:15] up_vect; down_vect[lsb_base_expr +: width_expr] up_vect [msb_base_expr +: width_expr] down_vect[msb_base_expr…
e19293001
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ADDRESS WIDTH from RAM DEPTH

I am implementing a configurable DPRAM where RAM DEPTH is the parameter. How to determine ADDRESS WIDTH from RAM DEPTH? I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH) i.e ADDRESS WIDTH = log (base 2) RAM DEPTH. How to implement the log (base 2)…
Ashwini
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Assign a synthesizable initial value to a reg in Verilog

I'm an FPGA noob trying to learn Verilog. How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant. I'm trying to do something like this in the code below. I get an error because the 8 bit constant…
Frank Dejay
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