Stack Overflow
Stack Overflow

Questions tagged [timing-diagram]

11 questions
155
votes
5 answers

How can I reduce the waiting (ttfb) time

I have a query which involves getting a list of user from a table in sorted order based on at what time it was created. I got the following timing diagram from the chrome developer tools. You can see that TTFB (time to first byte) is too high. I…
govindpatel
  • 2,539
  • 2
  • 19
  • 20
49
votes
9 answers

Drawing Sequence Diagrams

I'm looking for an easy language/command line utility to draw sequence and timing diagrams (could be 2 different tools). I've already found Mscgen for sequence diagram drawing and looks pretty good, but I'm studying other possibilities. Thanks
rnunes
  • 2,785
  • 7
  • 28
  • 56
33
votes
14 answers

Tool for drawing timing diagrams

Recently I am working with a hardware design group developing an ASIC. And I am drawing a lot of timing diagrams for which I am using Microsoft Excel, as it is easy to import into Word document. But, things are getting more and more difficult with…
Alphaneo
  • 12,079
  • 22
  • 71
  • 89
2
votes
1 answer

Comprehensive list of Tikz-timing options

Anyone here a guru in Tikz-timing? I am looking for a way to label a timing diagram with annotations, but the vertical scale is too compressed. I couldn't find a comprehensive list of options for the \timing command (or if I did, it was a meager…
vo1stv
  • 55
  • 2
  • 17
1
vote
0 answers

Is it possible to use multiple overlaping math/data curves inside one row?

I want to recreate something like this multyple functions, multiple states per row in WaveDrom like they do in PlantUML: So to have: Multiple math/data functions per row Scales for that data/functions How to do such thing in wavedrom?
DuckQueen
  • 772
  • 10
  • 62
  • 134
1
vote
1 answer

Why do verilog tutorials commonly make reset asynchronous?

This question is in the context of FPGA synthesis if that makes any difference. The data sheet (iCE40UP) states that each logic cell has a D-type flop with asynchronous reset and clock enable inputs. Many verilog tutorials introduce sequential logic…
Marsh Ray
  • 2,827
  • 21
  • 20
1
vote
1 answer

timing diagram of Memory Read Cycle in 8085 Microprocessor

From the topic of Memory Read Machine Cycle, I got an example of timing diagram for MVI instruction. Again in another topic Memory Interfacing, the book shows timing diagram of Memory Read Cycle. Here 8085 provides two signals – IO/M(bar) and…
user4221591
  • 2,084
  • 7
  • 34
  • 68
0
votes
1 answer

What book should I refer for flip flop timing diagram for VLSI (for such question given below)?

enter image description here I am pursuing masters in electronics system design and this was my question paper for today exam was unable to answers the first three questions properly.
Varun
  • 21
  • 7
0
votes
0 answers

Has Anyone Seen or Have an APNS Network Timing Diagram?

What: Need a network timing diagram showing the TCP ports and direction of communications (who does initial SYN to whom) between Mobile Device Management (MDM) server, the Apple Push Notification Server (APNS) and the client iOS device. Why: In…
Cerniuk
  • 14,220
  • 2
  • 29
  • 27
0
votes
1 answer

VHDL code runs but timing diagram shows nothing

I am trying to implement a cache memory 16 * 37 in VHDL in DesignWorks 5. The code is given below. The code runs but when i change values from IO panel or even simulate anyway, the timing diagram shows nothing and basically the code is not running…
NoorUllah
  • 621
  • 1
  • 5
  • 7
-1
votes
1 answer

Google chrome first request on fresh start take a long queuing time

For some weeks now (didn't happened before) Google Chrome takes a long time to respond on first request. To reproduce : Close Google Chrome Open Google Chrome Open any website The first request will take more than 10s, sometime 12s, sometimes 15s,…
Rexave
  • 367
  • 1
  • 3
  • 15