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Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

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Better way of coding a RAM in Verilog

Which code is better in writing a RAM? assigning data_out inside always block: module memory( output reg [7:0] data_out, input [7:0] address, input [7:0] data_in, input write_enable, input clk ); reg [7:0] memory [0:255]; …
e19293001
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How to sign-extend a number in Verilog

I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got so far: [EDIT: Changed the selection statement slightly] `timescale 1ns / 1ps module SignExtender( CLK, extend, extended…
Alex Mullans
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How to use clock gating in RTL?

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk &…
newbie
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test bench for writing verilog output to a text file

i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while writing it to text file im getting XX for every input. may be there is some syntax error or some other. if any can help plz write down test bench…
user3432905
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Verilog to GDSII compiler (open-source)

May be this question a bit not for StackOverflow, but both compilers and Verilog (which can be considered as programming language) are related to this project. Where can I find a open-source (or downloadable and free-to-noncommercial-use) compiler…
osgx
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Differences between Wallace Tree and Dadda Multipliers

Could anyone tell the difference in the partial products reduction method or mechanism between Wallace and Dadda multipliers ? I have been reading A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf
kevin998x
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What is difference between index(9) and index(9 downto 9) in vhdl?

logic index : unsigned(9 downto 0) ; type fft_data is array (3 downto 0) of unsigned(16 downto 0); signal tmp,signal fmax_data :fft_data; tmp = fmax_data(to_integer(index(9))); Above part of the code gives following compilation error;…
user2624915
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Shift Registers Verilog

I am very new to HDL language. I have a question about how to program a shift register. (i know i shift to the other direction). Why does the book use wire[N-1:0] r_next? what's drawback of my implementation? thanks my first try is as…
Grey
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how can I apply fixed fraction to the integer

I'd like to multiply to integer with modified fraction as following (Multiplication by power series summation with negative terms) I have done what to find the method the fraction convert to CSD form. But I want to know how can I apply to multiply…
BONGKA
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Multiplication by power series summation with negative terms

How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again. For example 0.3545 = 2^-2 + 2^-4 +…
BONGKA
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OASIS VLSI layout files parser

OASIS is a format for VLSI topology representation. I need a parser for the OASIS format, or maybe some documentation which will describe how this format is structured. I can't find any mentions of it in Google. Is there an OASIS parser available…
Alex Hoppus
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Error: (vlog-2110) Illegal reference to net "code"

I have tried this code, but it shows the error: gray_counter\gray_counter.v(2): (vlog-2110) Illegal reference to net "code" module gray_counter(code,clk,rst,count);//module declaration input [2:0]code=3'b000; input clk,rst; output reg count; …
kaviyarasu s
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Processing - interactive graphics editor

I'm involved in developing a free on line academic instructional tool which can be used by students of VLSI Engineering. I have decided to use Processing to develop the program. Central to the application is the ability of the user to draw some…
Dhruv
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is there any possibility for "if" block to go out of given choices in vhdl?

Below is the code of VHDL which uses IF block. In the last "elsif", the value of "my_choice" is assigned to "ch4". Then "else" block is executed, since no condition is satisfied. But, is there any chance that "my_choice" gets some other value other…
Raviteja
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System Verilog always_latch vs. always_ff

I am confused about the usage of statements always_ff and always_latch. The former would be used as: always_ff @ (posedge clk) begin a <= b; end while the latter: always_latch begin a <= b; end The first is activated just by the positive…
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