Highest Voted 'asic' Questions

33

votes

14 answers

Tool for drawing timing diagrams

Recently I am working with a hardware design group developing an ASIC. And I am drawing a lot of timing diagrams for which I am using Microsoft Excel, as it is easy to import into Word document. But, things are getting more and more difficult with…

asked Oct 06 '09 at 08:14

Alphaneo

12,079
22
71
89

9

votes

4 answers

Is it necessary to seperate combinational logic from sequential logic while coding in VHDL, while aiming for synthesis?

I am working on projects which requires synthesis of my RTL codes specifically for ASIC development. Given the case, how much important is it, to separate sequential logic from differential logic while designing my RTLs ? And if it is important,…

vhdl register-transfer-level asic soc

asked Apr 17 '17 at 12:39

Gaurav Singh

127
9

9

votes

2 answers

What is the practical difference between implementing FOR-LOOP and FOR-GENERATE? When is it better to use one over the other?

Let's suppose I have to test different bits on an std_logic_vector. would it be better to implement one single process, that for-loops for each bit or to instantiate 'n' processes using for-generate on which each process tests one…

for-loop vhdl fpga hardware asic

asked Jul 13 '15 at 21:16

Felipe GM

129
1
8

6

votes

2 answers

Doxygen alternative for Verilog, SystemVerilog?

Project "doxverilog" is not supported more, author's site is not responding. Project http://intelligentdv.com/downloads/index.html#doxygentools works only for SV class hierarchy. AMIQ http://www.dvteclipse.com/ Specador is enterprise overpriced…

verilog doxygen fpga system-verilog asic

asked Apr 22 '15 at 12:07

Mike I.

91
1
2
5

6

votes

6 answers

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry…

verilog vhdl system-verilog fpga asic

asked Apr 27 '10 at 15:01

Brian Carlton

7,545
5
38
47

5

votes

4 answers

Do all Flip Flops in a design need to be resettable (ASIC)?

I'm trying to understand clock-reset in a chip. In a design what criteria are used to decide whether a flop should be assigned to a value (typically to zero) during reset? always_ff @(posedge clk or negedge reset) begin : process_w_reset …

vhdl verilog system-verilog asic

asked Apr 11 '15 at 04:02

newbie

4,639
10
32
45

5

votes

3 answers

Fast way of multiplying two 1-D arrays

I have the following data: A = [a0 a1 a2 a3 a4 a5 .... a24] B = [b0 b1 b2 b3 b4 b5 .... b24] which I then want to multiply as follows: C = A * B' = [a0b0 a1b1 a2b2 ... a24b24] This clearly involves 25 multiplies. However, in my scenario, only 5…

hardware vhdl verilog fpga asic

asked Apr 11 '13 at 15:48

trican

1,157
4
15
24

5

votes

1 answer

relationship between flopping and meta-stability

While doing clock domain conversions (rate matched) we usually double flop the data to avoid meta-stable states. Double flopping just reduces the probability of meta-stability. Triple flopping will reduce it further. How to calculate the…

fpga asic

asked Aug 22 '12 at 06:43

arun

55
1
6

4

votes

1 answer

How to define default value for record type

Is it possible to define a default value for a record type or generally any user defined type? Something like (pseudo VHDL): type t_foo is record a : integer := 4; b : std_logic := '0'; end record; or subtype glarp is integer range 0 to 10…

vhdl fpga asic

asked Mar 30 '19 at 20:28

andrsmllr

1,231
18
39

4

votes

4 answers

how to track errors in FPGA/ASIC development using post place'n' route and/or post synthesis simulation?

I am a bit confused on the usefulness of post PnR and/or post synthesis simulations for FPGA/ASIC development. If the synthesis or PnR process complete successfully in the design flow, is there any chance that the respective 'post' simulation will…

simulation fpga synthesis asic

asked Aug 02 '17 at 18:21

user2609910

157
8

4

votes

3 answers

Systemc Error with the library

I installed the SystemC library 2.3.1 using this tutorial. I wrote this hello world example: //hello.cpp #include SC_MODULE (hello_world) { SC_CTOR (hello_world) { } void say_hello() { cout << ”Hello World systemc-2.3.0.\n”; …

c++ hardware fpga systemc asic

asked Jul 13 '16 at 13:14

Álison Venâncio

80
1
7

3

votes

2 answers

Difference between process and "vanilla" VHDL

I'm practicing VHDL, and I have a fundamental question about "simple" statements which do not require a process. I would like to know the difference between c <= a and b; Where the statement is not inside a process, just written after the…

vhdl fpga hardware asic

asked Oct 03 '18 at 08:07

graille

1,131
2
14
33

3

votes

1 answer

Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment

If for a given process, I declare a variable (let's say a 1 bit variable, variable temp : std_logic;) then can I assign a value to the variable if a given condition returns true, i.e. if (xyz=1) then --Assuming that this condition returns…

vhdl synthesis register-transfer-level asic soc

asked Apr 22 '17 at 13:43

Gaurav Singh

127
9

3

votes

2 answers

Creating pulses of different width

I have written following code which produces pulse of different width.I want the code to produce a single pulse according to select line. If select line is 00 pulse width = 1 us , 01 pulse width = 10 us …

verilog register-transfer-level asic

asked Aug 26 '15 at 04:58

Ishita Shah

99
1
4
12

3

votes

1 answer

Synopsys design compiler- view datapath extraction results

I am using Synopsys Design Compiler(SDC) for synthesis with compile_ultra. This option does advanced datapath extraction which basically tries to group(or chain) together as many arithmetic operations as possible and then uses carry-save arithmetic…

vhdl synthesis asic

asked Jul 30 '14 at 14:24

shrm

1,112
2
8
20

Questions tagged [asic]