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Questions tagged [synthesis]

Synthesis turns a high level circuit description into an implementation in logic gates.

Synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) described in VHDL or Verilog, is turned into a design implementation in terms of logic gates.

Wikipedia

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Convert Mat to Array/Vector in OpenCV

I am novice in OpenCV. Recently, I have troubles finding OpenCV functions to convert from Mat to Array. I researched with .ptr and .at methods available in OpenCV APIs, but I could not get proper data. I would like to have direct conversion from Mat…
Main
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Sound generation / synthesis with python?

Is it possible to get python to generate a simple sound like a sine wave? Is there a module available for this? If not, how would you go about creating your own? Also, would you need some kind of host environment for python to run in in order to…
Alex Coplan
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How to override a superclass' property with more specific types?

The Scenario I have a situation where a base class called AbstractRequest has a delegate property of type id declared in the header file: @property (nonatomic, assign) id delegate; The abstract…
epologee
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@property and @synthesize in objective-c

While I was playing and figure out how things work in https://github.com/enormego/EGOTableViewPullRefresh I found mysterious of @property and @synthesize. Here is the code I mentioned EGORefreshTableHeaderView.h @interface EGORefreshTableHeaderView…
sarunw
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I want to learn audio programming

At my high school we can take a class where we basically learn about a subject on our own for a semester. I was thinking that I want to learn about "sound programming," but I realized that I have no idea what that entails. I'm interested in learning…
Austin Gayler
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How to reproduce C64-like sounds?

I did some of my own research and found out that SID-chips had only few hardware supported synthesizing features. Including three audio oscillators with four possible waveforms (sawtooth, triangle, pulse, noise), with ADSR envelopes and ring…
Cheery
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Why is rising edge preferred over falling edge

Flip-Flops(,Registers ...) are usually triggered by a rising or falling edge. But mostly in code you see an if-clause which uses the rising edge triggering. In fact i never saw a code with falling edge. Why is that? Is it because naturally the…
hr0m
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Verilog sequence of non blocking assignments

Say the following code section (same block): A <= 1 A <= 2 Will variable A always be assigned 2? or will there be a race condition and 1 or 2 will be assigned ? My understanding of non blocking assignment is that it is up to the hardware to assign…
nehz
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@property and @synthesize

I'm very new to Objective C. (Two days now). When read about @synthesize, it seemed to overlap with my understanding @property (which I thought I understood) ... So, some details need to be ironed out in my mind ... it's bugging me. Please…
RichWalt
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Android Audio - Streaming sine-tone generator odd behaviour

first time poster here. I usually like to find the answer myself (be it through research or trial-and-error), but I'm stumped here. What I'm trying to do: I'm building a simple android audio synthesizer. Right now, I'm just playing a sine-tone in…
Tsherr
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Frequency Modulation Synthesis Algorithm

Based on what I read, I've made an algorithm for FM sound synthesis. I'm not sure if I did it right. When creating a software synth instrument a function is used to generate an oscillator and a modulator can be used to module the frequency of this…
Matthew Mitchell
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Is $readmem synthesizable in Verilog?

I am trying to implement a microcontroller on an FPGA, and I need to give it a ROM for its program. If I use $readmemb, will that be correctly synthesized to a ROM? If not, what is the standard way to do this?
user526035
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In SystemVerilog, is it allowed to read a parameter from an interface

I am a bit confused as to if it is legal, from a standards stand point, to read a parameter from an interface. Like so interface foo_if #(parameter BAR=5)(); ... logic [BAR-1:0] data; modport slave(input data, ...); endinterface module…
AxelOmega
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Continuous waveform audio synthesizer

I'm starting to write a soft synthesizer with a peculiar characteristic: The oscillators will have a "continuous waveform" knob that will allow users to select sine, square and saw tooth waves in a continuous fashion. That is, if the knob is all the…
Rafael Vega
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What happens when an integer goes out of range in VHDL?

Let's say you have a signal defined as follows: signal test_count : integer range 0 to 11; Now if test_count ever goes below 0 or above 11 in simulation it will cause the simulation to crash immediately. What I'm wondering is what happens when…
Russell
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