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I'm practicing VHDL, and I have a fundamental question about "simple" statements which do not require a process.

I would like to know the difference between

c <= a and b;

Where the statement is not inside a process, just written after the architecture begin, and

process(a,b)
begin
    c <= a and b;
end process;

Will these results produce the same thing? Ty :)

graille
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  • The first form is a syntactic sugar of the latter form. – Paebbels Oct 03 '18 at 13:42
  • IEEE Std 1076-2008 11.6 Concurrent signal assignment statements "A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals.", "The process statement equivalent to a concurrent signal assignment statement whose target is a signal name is constructed as follows:...", 14.2 Elaboration of a design hierarchy "The elaboration of a design hierarchy creates a collection of processes interconnected by nets; this collection of processes and nets can then be executed to simulate the behavior of the design." –  Oct 03 '18 at 18:07
  • And the telling (11.6) "Execution of a concurrent signal assignment statement is equivalent to execution of the equivalent process statement." –  Oct 04 '18 at 01:46

2 Answers2

2

Yes, the two descriptions are equivalent.

The concurrent signal assignment c <= a and b is evaluated at each update of any of the argument (a or b), and the process will also evaluate each time any of the arguments in the sensitivity list is updated (a or b).

In the simple example it not required to use a process, but for more complex expressions, the process has the advantage that control structures like if and for can be used, which is not directly possible in a concurrent signal assignment. Also, for sequential logic a process is required.

Morten Zilmer
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    "_`process` has the advantage that control structures like `if` and `for` can be used_": OK for the loops but concurrent signal assignments can also implement `if-elsif-elsif-else` (`sig <= val1 when cond1 else val2 when cond2...`) or `case` control structures (`with...select`). – Renaud Pacalet Oct 03 '18 at 09:20
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    "_for sequential logic a process is required_": what about `Q <= D when rising_edge(CLK);`? – Renaud Pacalet Oct 03 '18 at 09:21
  • @RenaudPacalet: Thanks for the additions. I agree that `when-else-...` can substitute `if-then-...` for concurrent assign. Also, if `if-then-...` is wanted in concurrent assign, then these can be wrapped in a function, so yet another example of how to do without `process`. For sequential logic I will oppose the concurrent assign using `Q <= D when rising_edge(CLK);`, since tools are likely to fail this; for example Intel Quartus 18.1 synthesis crashes when this construction is presented, thought is legal code, and ModelSim accepts it. – Morten Zilmer Oct 03 '18 at 17:38
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    The form `Q <= D when rising_edge(CLK);` was supported by Altera Quartus II. If Intel Quartus Prime does not accept this, it's a bug introduced into Quartus. It's also supported by Xilinx ISE, Xilinx Vivado and Lattice LSE. It's even possible to write own `rising_edge` functions. This is synthesized correctly in all mentioned tools except for Vivado, which creates latches instead of FFs... – Paebbels Oct 03 '18 at 17:52
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    @Paebbels: To double check if this is a Quartus 18.1 problem, I made a module with only two FFs, one as process and one as concurrent assign using above, and it breaks with "Internal Error: Sub-system: BPM, File: /quartus/db/bpm/bpm_hard_block_util.cpp, Line: 3458 ... Quartus Prime Information ... Version: 18.1.0 Build: 625 Edition: Lite Edition". ModelSim handles it nicely, showing same behaviour, and when I change the concurrent FF to process like then other it also runs through Quartus. I can send you my example, but not much to it. I will try to report to Intel. – Morten Zilmer Oct 03 '18 at 18:49
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You can think of any VHDL one liner as an implied process with the arguments on the RHS of <= in the sensitivity list. This is why both of the code snippets you wrote are practically equivalent.

shaiko
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