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Questions tagged [vpi]

Verilog Programming Interface. Also for PLI questions. Please provide details on the simulator you are working with.

VPI - Verilog programming interface.
PLI - Programming Language Interface

VPI is also known as PLI-2. VPI deprecates the original PLI interface.

VPI provides a generic interface to Verilog simulators that allows a user to query and manipulate the simulators data structures. VPI is conceptually similar to a compiler plug-in. Simulators do not produce (synthesize) final designs, but provide facilities for functional testing and verification. VPI can amend a simulation to give pseudo-timing information, to generate test vectors, and reports on Verilog code.

See: VPI at Wikipedia.

An example of using VPI with the open source simulator iverilog.

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Reading array of regs using Verilator and VPI

So I have the following register defined in my verilog reg [31:0] register_mem [0:15]/* verilator public */; My goal is from my verilator c++ code to read each of the 16 values stored in it. I have found that the documentation for this VPI stuff is…
J.Doe
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Obtaining signal names in the design (using VPI calls)

I would like to get a list of signal names in a given design hierarchy from a Verilog design using vpi. It is a simple net name browser interface from my custom tool that is written in C and Python. How can I get a list of signal names from a…
user2756376
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SystemVerilog VPI release a callback handle after a vpiForceFlag

When I asked SystemVerilog looping through hierarchy I was suggested to use a SystemVerilog VPI code to solve it. I posted my attempt but realized that after forcing the net value I need to release it.…
vrleboss
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What API to use for a Verilator test harness?

Verilator can output SystemC or C++ classes. There is a 'Verilator' API and I can find the headers, but they are just raw classes with no documentation. Some code looks like classes that are used directly by the backend to achieve the simulation…
artless noise
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Is it possible to iterate systemverilog associative array with non-int index type through VPI c function?

For example // test.sv class cls; int b; endclass module m cls testObj; int map[cls]; initial begin inst = new; inst.b = 10; map[cls] = 12; $VPIcall; end endmoudle // pseudocode vpi c vpiHandle…
tarik jhin
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SystemVerilog looping through hierarchy

I have registers instantiated in a Register block Regblock as such: DUT.Regblock.Register1 DUT.Regblock.RegisterA DUT.Regblock.RegisterABC ... All these registers have the same inner structure. I would like to simulate the effects of bit flips in…
vrleboss
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Pass an array element to vpi_handle_by_name

My test.sv code contains interface and module as shown: interface Bus; logic [7:0] sig1; logic [15:0] sig2; logic sig3; endinterface module test(); Bus inst(); ... endmodule I have given the vpiFullName test.inst.sig1 to the…
anu
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Call task or function via VPI

I know that it's possible to change the values of signals and variables via the Verilog Programming Interface (VPI). It's also possible to trigger a named event, by doing a vpi_put_value(...) on it. Is it somehow possible to call a function or to…
Tudor Timi
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How to read memory value at a specific location using VPI and verilator?

I want to trace the memory value at specific locations during simulation of a hierarchical design using Verilator. A short version of the memory model is defined as follows `module tc_sram{ parameter int unsigned NumWords =…
Sarah_lan
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Time unit for VPI call back on signal value change

In my VPI call back function, I am getting real value for time, but units for this time value depends on timescale for the module where signal resides. How I can find what units for the provided time? Here is my monitor VPI…
albert waissman
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In Verilog Procedural Interface, is it possible to scan through iteration loop several times?

We can use vpi_scan in the following way: vpiHandle iter = vpi_iterate(property, handle); if (iter) while ( entry = vpi_scan(iter) ) /*code*/; iter will be freed when vpi_scan() returns NULL. But what if I need to scan through the loop…
TT_ stands with Russia
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How to add a new key to a Systemverilog associative array using VPI

I'm trying to access Systemverilog associative array from C using VPI. I can write a value to an array element for a key using the following code if the key is already there. index = vpi_handle_by_index(reg_array, 200); // 200 is an existing…
user2756376
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How to check if a Systemverilog associative array has a key using VPI

I'm trying to access Systemverilog associative array from C using VPI. I can access the array element for a key using the following code if I provide an existing key. index = vpi_handle_by_index(reg_array, 200); // 200 is a valid…
user2756376
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Allocated structure for value_p to be used with VPI vpi_put_value()

I'm implementing Verilog "force" and "release" using VPI so that they can be called from C routines. To force a value to a vector net, I need to create an array of s_vpi_vecval for value_p. I allocated a storage for the array and populated it with…
user2756376
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How to get dimensions of a verilog vector port using PLI routines?

How can I fetch the dimensions of a vector port using the vpi PLI routines? For example, for the vector port declaration "output [2:1] out;", how can I get the left dimension as 2 and right dimension as 1? I tried using vpiRange property but it…
Saurabh
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