SystemVerilog looping through hierarchy

Question

I have registers instantiated in a Register block Regblock as such:

DUT.Regblock.Register1
DUT.Regblock.RegisterA
DUT.Regblock.RegisterABC
...

All these registers have the same inner structure. I would like to simulate the effects of bit flips in these registers.

//Here an attempt to do bit flips
bitFlipLocation = $random;
force  DUT.RegBlock.Register1.reg[bitFlipLocation] = ~DUT.RegBlock.Register1.reg[bitFlipLocation];
release DUT.ABCStar1.RegBlock.Register1.reg[bitFlipLocation];

Is there a way to create a loop over all DUT.Regblock.Register1, RegisterA, RegisterABC, ... inside RegBlock and create these bit flips?

no, there is no such way in system verilog, unless you re-declare all those variously-named registers as a some type of an array. So, but now the question is: _what is the **Register**_? is it a data struct or a module, or a block? — Serge, Aug 23 '17 at 18:40
in this case you might want to look into arrayed instantiations and generate blocks. However, it could be a mess and the only reason to go there if you need a synthesizable model. otherwise, use Daves suggestion. — Serge, Aug 23 '17 at 20:47

score 3 · Accepted Answer · answered Aug 23 '17 at 16:57

3

There are ways to do this, but not within the SystemVerilog language itself. You can write VPI code in C to iterate over block names and apply the forces use the C API. Or you can use tool specific commands to iterate of block names and use commands (usually Tcl) to apply the forces.

Both of those are beyond the scope of what can be shown in this forum.

answered Aug 23 '17 at 16:57

dave_59

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Wouldn't enabling UVM and using the `uvm_hdl_*` methods suffice? – Greg Aug 23 '17 at 17:56
Yes, that is essentially the same as using the VPI. OP did not reveal if they were already using the UVM. – dave_59 Aug 23 '17 at 18:50
@dave_59 pointed me in the right direction - I am now trying to implement the solution and will post it here when I succed. I am not currently using UVM but if the implementation is simple I am interested in learning it. – vrleboss Aug 23 '17 at 19:04
using 'c/c++' instead of uvm functions will make it a bit more efficient though. You can do it from a dpi call. . – Serge Aug 23 '17 at 20:50

vrleboss · Answer 2 · 2017-08-28T05:02:11.827

Following dave's answer I implemented the VPI code in C to loop over all register within RegBlock and randomly force bit flips at some positions (register is 32 bit wide).

#include <sv_vpi_user.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#define NULL 0

void reg_flips() {
  vpiHandle module_iter;
  vpiHandle module_obj;
  vpiHandle module_regblk;
  vpiHandle reg_nets;
  vpiHandle net;
  //Starting from the RegBlock
  module_regblk = vpi_handle_by_name("DUT.RegBlock",NULL);
  //Iterator over all register in RegBlock
  module_iter = vpi_iterate(vpiModule,module_regblk);
  while (module_iter) {
    module_obj = vpi_scan(module_iter);
    if (module_obj) {
      reg_nets = vpi_iterate(vpiReg,module_obj);
        while (reg_nets) {
          net = vpi_scan(reg_nets);
          if (net) {
            s_vpi_value val;
            val.format = vpiIntVal;
            val.value.integer = rand()%2;
            int position = rand()%32;
            //Forcing the value at a given position.
            vpi_put_value(vpi_handle_by_index(net,position),&val,NULL,vpiNoDelay);
          }
          else {
            reg_nets = NULL;
          }
        }
      }
    }
    else {
      module_iter = NULL;
    }
}

SystemVerilog looping through hierarchy

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