Icarus Verilog is an implementation of the Verilog HDL or hardware description language.
Icarus Verilog is the same as iverilog
Questions tagged [icarus]
70 questions
6
votes
2 answers
Icarus verilog dump memory array ($dumpvars)
I try to dump an array (reg [31:0] data [31:0]) but I can't do it successfully.
I've tried the way that is in the iverilog wiki:
integer idx;
for (idx = 0; idx < 32; idx = idx + 1)
$dumpvars(0,cpu_tb.cpu0.cpu_dp.cpu_regs.data[idx]);
It works,…
gon1332
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6
votes
2 answers
Gallio Icarus vs. Testdriven.net
What are the differences between using a VS integrated tool like Testdriven.net or using a GUI test runner like Icarus or NUnit GUI?
What do you prefer and why?
So far i've found that reports are better in Icarus than in td.net, which only features…
Johannes Rudolph
- 35,298
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5
votes
3 answers
Simple Verilog VPI module to open audio files
I would like to write a VPI/PLI interface which will open audio files (i.e. wav, aiff, etc)
and present the data to Verilog simulator. I am using Icarus at the moment and wish to
use libsndfile to handle input file formats and data type…
errordeveloper
- 6,716
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4
votes
1 answer
Always vs forever in Verilog HDL
What are the difference between the always keyword (not the always @ block) and forever keyword in Verilog HDL?
always #1 a=!a;
forever #1 a=!a;
Here are my findings but I can't still quite draw the line between the two:
From Wikipedia:
The always…
ellekaie
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4
votes
3 answers
Debugging combinational logic loops in Icarus Verilog
I'm using Icarus verilog to simulate a reasonably complex design. I find that in some rare cases my simulation gets "stuck", i.e., the clock doesn't tick any more and none of the signals appear to change. I suspect this is because I have a…
Pramod
- 9,256
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3
votes
1 answer
How can I output a value to a register with a Verilog task?
My understanding of Verilog tasks is that they act like subroutines and are able to accept both input and output parameters. Using $display, I can peek at the values of my register variables along the way. For some reason my output register does not…
Nathan Farrington
- 1,890
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3
votes
1 answer
How to know which simulator is used in cocotb testbench?
To test my Verilog design I'm using two differents simulators : Icarus and Verilator. It's work, but there are some variations between them.
For example, I can't read module parameter with verilator, but Icarus works.
Is there a way to know which…
FabienM
- 3,421
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- 45
3
votes
2 answers
SystemVerilog support of icarus (iverilog compiler)
I am using iverilog on a Mac, and I have problem compiling some codes that include always_ff and always_comb blocks. ModelSim compiles those codes without any problem. Is it possible to configure iverilog so as to support always_ff and always_comb…
k.rallis
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- 1
- 3
2
votes
1 answer
How to include files in icarus verilog?
I know the basic `include "filename.v" command. But, I am trying to include a module which is in another folder. Now, that module further includes other modules present in the same folder. But, when I try to run the module on the most top-level, I…
Harshit Gupta
- 51
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1
vote
1 answer
Error: "Syntax in assignment statement l-value." while trying to assign a reg inside an always block
I'm trying to model a circuit. Here is the code of the circuit I'm trying to build. I get the error inside the always block and specifically inside the cases. I'm trying to assign reg NextState to a specific state;
however I get an error.
module…
1
vote
1 answer
icarus verilog: Unable to bind variable
I am trying to pass a string as parameter to a module and getting this error:
Unable to bind variable
module dut #(parameter string CONFIG_FILE)
(
input logic clk
);
endmodule
module main;
localparam string CONFIG_FILE = "Config.txt";
logic…
nir
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1
vote
1 answer
reg qb; cannot be driven by primitives or continuous assignment
I'm trying to make an SR flipflop on Icarus Verilog.
Flipflop module:
module srff(sr,clk,q,qb);
input [1:0]sr;
input clk;
output reg q,qb;
always@(posedge clk) begin
case(sr)
2'b00: q=q;
2'b01: q=0;
…
Prerk
- 55
- 9
1
vote
1 answer
When simulating verilog output using Icarus, is there a way to include FPGA hardware features such as RAM in the simulation?
I'm new to FPGA, and have started out with an iceBreaker board using the ICE40UP5K chip. I'm aiming to make a LED display driver, driving something similar to HUB75 used on popular display modules.
I've been able to simulate waveform generation, and…
MickJC75
- 39
- 4
1
vote
1 answer
Testing multiple configurations of parameterizable modules in a Verilog testbench
Say I have a Verilog module that's parameterizable like the below example:
// Crunches numbers using lots of parallel cores
module number_cruncher
#(parameter NUMBER_OF_PARALLEL_CORES = 4)
(input clock, ..., input [31:0] data, ... etc);
…
John M
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1
vote
1 answer
Verilog module not being called
I'm working on a program that will take a value in BCD, convert it to binary, and count down for the given value to 0. The BCD conversion module works perfectly, but it seems my 'microwave' module is not being called.
My output of this program…
Jmerlok
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