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Questions tagged [cocotb]

Cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL hardware designs using Python.

Cocotb is a COroutine based COsimulation TestBench environment for verifying / RTL using .

Documentation is at https://cocotb.readthedocs.io

Support via the Gitter channel https://gitter.im/cocotb or the mailing list at https://lists.librecores.org/listinfo/cocotb

44 questions
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How to inject Verilog code in Chisel generated Module?

To test my Chisel designs I'm using Icarus with cocotb. But Icarus doesn't generate VCD traces if it's not asked explicitly in verilog module code like this : `ifdef COCOTB_SIM initial begin $dumpfile ("my_module_name.vcd"); $dumpvars (0,…
FabienM
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Cocotb VHDL need for FLI

I am currently setting up a Cocotb based verification environment. I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface). I get the following…
user1654361
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How to force usage of python 3 in cocotb?

I'm using CocoTB to test my HDL design, but as I understand, it's possible to use it with python2.7 or python3. In setup.py config file I can see that both are supported : [...] "Programming Language :: Python :: 2.7", "Programming…
FabienM
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How do I specify the compare function of the scoreboard in Cocotb?

I want to extend the Endian Swapper example of Cocotb, so that, it also checks the contents of the packages outputted by the device under test (DUT). In the provided example code, the model function which generates the expected output appends the…
Martin Zabel
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How to know which simulator is used in cocotb testbench?

To test my Verilog design I'm using two differents simulators : Icarus and Verilator. It's work, but there are some variations between them. For example, I can't read module parameter with verilator, but Icarus works. Is there a way to know which…
FabienM
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Modify VHDL generic value with ghdl in cocotb

I managed to read generic module value with cocotb without problem. But if I can't manage to write it. My VHDL generic is : ... generic ( ... C_M00_AXI_BURST_LEN : integer := 16; ... ) I can read it in cocotb: …
FabienM
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1 answer

Verilog with cocotb : assign statement

My Verilog code is an adder that just uses assign sum = a+b. The problem is that, while running it using cocotb, sum remains unknown, though a and b have valid values. When I make sum a reg type, it works. `timescale 1 ns / 1 ps module adder(input…
n.r
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Cocotb coroutine never called

I just started using cocotb and I have a problem with a small piece of code that should use a coroutine. import cocotb from cocotb.triggers import Timer @cocotb.coroutine def test(dut): dut.a <= 1 dut.b <= 2 cocotb.log.info('test') …
mdxg
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GHDL, Precompile Vendor Primitives and Cocotb

I have a design where I use an IP module generated by Lattice Diamond. This uses the Macxo3l library which is shipped with diamond as a vendor library. Using GHDL I can compile the design including this library using the instructions from…
kayakist
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Pass argument from makefile to cocotb testbench

Given the D-FF example from cocotb/examples/dff/. What is the proper way to pass an argument from the Makefile to the cocotb testbench dff_cocotb.py without modifying the native cocotb makefiles? I tried to modify line 30 of…
Marph
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Unusable module names with generate statement in cocotb

Im using cocotb v1.0 and ghdl 0.35-dev (llvm and gcc backend). The top level contains a simple for generate statement: gen_pe : for i in 1 to 4 generate ... end generate gen_pe; I tried to access the first generated module in my cocotb…
Marph
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How to reduce log line size in Cocotb

In cocotb testbench log printing in terminal have really long line : 28204007.00ns INFO cocotb.regression regression.py:341 in _log_test_summary …
FabienM
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How to print log message with cocotb

On the cocotb official quick start guide the method to print log message is to use _log.info() on the dut object : import cocotb from cocotb.triggers import Timer @cocotb.test() def my_first_test(dut): """ Try accessing the design """ …
FabienM
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Cocotb using generics/parameters in gate level simulation

I have successfully setup a Cocotb verification environment for my design, and I am happy the way it works for RTL (VHDL in my case). My design is using generics, and I am retrieving the value of these generics in several places of the python code…
user1654361
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2
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bus monitor for cocotb

I am trying to setup Cocotb as my verification environment. I have been looking at the examples, that are useful, but I am not sure about direction I should go. My block can be seen as: 4 busses in input 1 clock and 1 reset as inputs 2 busses…
user1654361
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