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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

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What benefits does Chisel offer over classic Hardware Description Languages?

Chisel is an alternative to classic Hardware Description Languages (HDLs) like Verilog and VHDL. My experience with Verilog and its existing prevalence in both industry and academia indicate that it is a well-developed mature language. Can someone…
Eric Wu
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Chisel: how to implement a one-hot mux that is efficient?

I have a table, where each row of the table contains state (registers). There is logic that chooses one particular row. Only one row receives the "selected" signal. State from that chosen row is then accessed. Either a portion of the state is…
seanhalle
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Learning Chisel -- advanced examples to understand Rocket Chip code

The Berkeley implementation of RISC-V is called Rocket Chip and it is written in a hardware language called Chisel. Chisel is object oriented, and it has been difficult for the people on our team to learn to the point of being effective at modifying…
seanhalle
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How to inject Verilog code in Chisel generated Module?

To test my Chisel designs I'm using Icarus with cocotb. But Icarus doesn't generate VCD traces if it's not asked explicitly in verilog module code like this : `ifdef COCOTB_SIM initial begin $dumpfile ("my_module_name.vcd"); $dumpvars (0,…
FabienM
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Is there a simple example of how to generate verilog from Chisel3 module?

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog. I take Gcd source code given on official web page of chisel. import chisel3._ class GCD extends Module { val io = IO(new Bundle { val a =…
FabienM
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What's the difference between Chisel and Lava and CLaSH?

I've been studying the sources of Chisel and also various Lavas (Kansas, Chalmers and Xilinx flavors) and CLaSH. I'm trying to understand what's the main selling points of Chisel versus the others. The main one I've identified is fast simulation. I…
Michael Fox
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How to find the number of PLIC contexts?

I'm a SW developer trying to understand configuration of the RISC-V Platform-Level Interrupt Controller (PLIC) that's in a rocket-chip derived SoC in an FPGA. Please correct me if my terminology is off. I'm trying to programmatically configure the…
Jens
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Why does sbt fail with "Expected ';'"?

When I run example chisel design from the learning-journey project, I am seeing error as following: $ ./run-examples.sh SimpleALU ... [info] Set current project to chisel-tutorial (in build file:/home/fchen/work/learning-journey/) …
Fei Chen
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Simulating a CPU design written in Chisel

I've written a single-cycled CPU in Chisel3 which implements most of the RV32I instructions (except CSR, Fence, ECALL/BREAK, LB/SB, which may be included later). The instructions are currently hard coded in the instruction memory, but I will change…
dannebra
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Converting Chisel to Vhdl and SystemC?

I have some question about Chisel conversion. I know it's theoretical but it would be nice if someone give his opinion. 1) I want to ask why Chisel does not focus on VHDL / SystemVerilog conversion. Although both Verilog and VHDL are same, in some…
ARK91
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What is Clone in Chisel

I am a new learner of Chisel. What is the purpose of Cloning in Chisel? I saw somewhere written, "it creates a shallow copy". Why do we need it? Here are examples. Could you please elaborate it. 1) class Valid[+T <: Data](gen: T) extends Bundle …
ARK91
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Chisel code transformation

So, I have a theoretical question about the Chisel code transformation. I know Chisel is actually a set of Scala definitions, so it is compiled to Java bytecodes, which in turn run in the JVM and, just like a magic, it spits out Verilog equivalent…
Rafael
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How to Initialize a Register of Vectors?

I have defined a register of vectors like this val my_reg = Reg(Vec(n, Bits(32.W))) and I access the elements of this register in a for loop using my_reg(i). Now, I like to initialize this register to zero, so I change the variable definition to…
Matt
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Syntax about chisel :Vec & Wire

I am learing Chisel3. I have some questions about the codes. val myVec = Wire(Vec(5, SInt(width = 23))) // Vector of 5 23-bit signed integers. I thought if I declare a vector and I need to write "Wire",but I was wrong when I saw these codes. class…
jjlin
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How to do a vector of modules?

I want to instantiate a one dimensional array of element, and element extends Module. How would I do this? If I say my best guess, which is: val elements = Vec( 64, new element ) I get the following error message: [error]…
Mykland
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