Stack Overflow
Stack Overflow

Questions tagged [rocket-chip]

Use for questions related to the Rocket-Chip SoC generator, used to generate and simulate multi-core RISC-V-based SOCs.

Resources

129 questions
9
votes
4 answers

Learning Chisel -- advanced examples to understand Rocket Chip code

The Berkeley implementation of RISC-V is called Rocket Chip and it is written in a hardware language called Chisel. Chisel is object oriented, and it has been difficult for the people on our team to learn to the point of being effective at modifying…
seanhalle
  • 973
  • 7
  • 27
7
votes
1 answer

How to find the number of PLIC contexts?

I'm a SW developer trying to understand configuration of the RISC-V Platform-Level Interrupt Controller (PLIC) that's in a rocket-chip derived SoC in an FPGA. Please correct me if my terminology is off. I'm trying to programmatically configure the…
Jens
  • 69,818
  • 15
  • 125
  • 179
5
votes
1 answer

firrtl.Driver is deprecated - but what should we use instead?

I've updated rocket-chip today and noticed that FIRRTL now says this: ------------------------------------------------------------------------------ Warning: firrtl.Driver is deprecated since 1.2! Please switch to…
jbaxter
  • 182
  • 10
5
votes
1 answer

How to iterate through similar registers definition in Chisel (regmap)

I have some similar register definition, and I want to write under the regmap construct. My code currently looks like this: val regs = RegInit(Vec(Seq.fill(5)(0.U(32.W)))) regmap ( ... 0x30 -> Seq(RegField(32,regs(0),RegFieldDesc("reg0",""), 0x34…
user3567895
  • 618
  • 3
  • 14
4
votes
2 answers

How to understand this line of chisel code

I'm in the process of learning chisel and scala language and try to analyse some lines of rocket-chip code.Could anyone try to explain me this line?…
nemanja
  • 75
  • 6
4
votes
1 answer

How to extract a standalone FPU module from Rocket-Chip Chisel code?

I am working on Rocket Chip Generator, which is a SoC written in Chisel. My objective is to extract the Floating-Point Unit, in order to synthesize it and study its power consumption/area ...etc. separately from the rest of the SoC. So I cloned the…
noureddine-as
  • 453
  • 4
  • 12
4
votes
3 answers

What is the meaning of :*= and :=* operators?

I see some examples in the RocketChip, but could not find info in the API reference masterNode :=* tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
Tampler
  • 385
  • 1
  • 9
4
votes
2 answers

How to add a sbus master to rocket-chip periphery

I'm trying to implement a DMA like periphery to the rocket chip. Meaning a module that is hooked to the pbus, and controlled by registers. it also has a master hooked to the sbus. I followed the sifive format to attach registers controlled…
user3567895
  • 618
  • 3
  • 14
3
votes
2 answers

Retrieve the reset value of RegInit

Is there a way to get the reset value of a RegInit by probing members of the type that is produces? I can see that a RegInit will return the type (e.g. UInt). For example I will have a register which I want to be controlled via a regmap val myRWReg…
l Steveo l
  • 516
  • 3
  • 11
3
votes
1 answer

IP block generation/testing when using diplomacy. Possible to give dummy node?

I've been studying rocket-chip for utilizing diplomacy and I have a decent grasp on the overall structure of how diplomacy works. (I don't understand it totally, but well enough to create some examples on my own). I would like to develop some IP in…
l Steveo l
  • 516
  • 3
  • 11
3
votes
1 answer

Response signal when performing a store into the L1 Dcache of Rocket Chip Core

If I perform a store into the L1 Dcache does the Rocket Chip core produce a resp valid signal or is that only for a load signal? Cos for a load signal you are requesting something and you get something in response whereas for the store you just need…
CV_Ruddha
  • 406
  • 2
  • 13
3
votes
2 answers

How to use Seq with Cat in Chisel?

I am learning chisel and rocket-chip. The rocket-chip has a code using Seq and Cat in RVC.scala. val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) But when I write my code as above, I got an Error. chisel reports type…
Self-Motivated Wu
  • 397
  • 2
  • 9
3
votes
2 answers

How to connect AHB port to DRAM controller device using Diplomacy

How do you connect from Rocket-Chip to an external AHB slave port (i.e., the AHB port on a memory controller)? I have tried to pattern my code after several other examples that connected to an AXI4 slave device, and that works ok. However, when I…
Adam Bryant
  • 53
  • 8
3
votes
0 answers

Dual port memories

I've managed to get Chisel to use a hard memory macro with the correct usage of a SeqMem() instance, but they're for single port memories only. Is there a way to get Chisel to infer a dual port memory macro?
jbaxter
  • 182
  • 10
3
votes
0 answers

Booting the Linux kernel on the Rocket Chip emulator

I'm trying to boot the Linux kernel in the generated Rocket Chip emulator using the DefaultConfig configuration. I'm following the steps shown in the RISCV tools repository wiki and I've been able to successfully build and boot the Linux kernel on…
poinu
  • 73
  • 1
  • 8
1
2 3
…
8 9