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Questions tagged [riscv32]

105 questions
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How to find the number of PLIC contexts?

I'm a SW developer trying to understand configuration of the RISC-V Platform-Level Interrupt Controller (PLIC) that's in a rocket-chip derived SoC in an FPGA. Please correct me if my terminology is off. I'm trying to programmatically configure the…
Jens
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Unsigned 64x64->128 bit integer multiply on 32-bit platforms

In the context of exploratory activity I have started to take a look at integer & fixed-point arithmetic building blocks for 32-bit platforms. My primary target would be ARM32 (specifically armv7), with a side glance to RISC-V32 which I expect to…
njuffa
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6
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2 answers

RISCV: how the branch intstructions are calculated?

I am trying to understand how modern CPU works. I am focused on RISC-V. there are a few types of branches: BEQ BNE BLT BGE BLTU BGEU I use a venus simulator to test this and also I am trying to simulate it as well and so far so good it works, but…
Kralik_011
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What is intended/correct way to handle interrupts and use the WFI risc-v cpu instruction?

I am very new to bare metal programming and have never delt with interrupts before, but I've been learning on a RISC-V FE310-G002 SOC powered dev board. I've been reading about the RISC-V WFI (Wait for interrupt) instruction and from the manuals, it…
Echelon X-Ray
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s-files generated from riscv-gnu-toolchain does not run RISCV emulator

I must compile a set of C++ files into RISC-V code (RV32IM). I am using riscv-gnu-toolchain and compiles with the following CMakeLists.txt file cmake_minimum_required(VERSION 3.10.2) project(project-title) set(CMAKE_CXX_FLAGS "-march=rv32im…
eirikvaa
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3
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Inline assemble(riscv32) in C

I try to realize inline assemble(riscv32) command in one program C and use litex to create the project in vivado and generate bin file. In simulation, part ASM does work (memory position x'10000400 does have value x'40) but when I implement in card…
KabiLink
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Better way to write a few MMIO register bits in RISC-V assembly?

To configure UART tx, water mark (0 to 7) has to be written on memory mapped tx control register on bit position [18:16]. My RISC-V assembly function first reads the present control register value, perform a bitwise AND with mask to clear bits…
RRON
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2 answers

Bare metal RISC-V CPU - how does the processor know which address to start fetching instructions from?

I am designing my own RISC-V CPU and have been able to implement a few instruction codes. I have installed the RV32I version of the GCC compiler and so I now have the assembler riscv32-unknown-elf-as available. I'm trying to assemble a program with…
Plasty Grove
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RISC-V Toolchain with Vector support

I am looking for a C/C++ toolchain that supports the RISC-V vector extension v1.0 as defined per official spec. Spike appears to support vector rvv1.0, but I am having trouble finding a toolchain to use it with. Neither GCC (I only see a branch for…
Fabian
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Where is the source code from the WCH RISC-V toolchain?

WCH, the company behind the famous 10-cent RISC-V microcontroller, has based its RISC-V toolchain on the xPack builds from Liviu Ionescu: https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/tag/v8.2.0-3.1/ Both output the same…
K.Mulier
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How do I write a bare-metal RISC-V program to go from boot to writing to the UART0 on QEMU's `sifive_e` machine?

Background I'm trying to understand the boot process for a simple RISC-V computer in detail. I'm not interested in getting all the way to an operating system: I just want to know what happens between poweron and running a bare-metal program to write…
statusfailed
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RISC-V assembler is replacing beq instructions by bne + jal

I have this RISC-V assembly program: addi x2,x0,5 addi x3,x0,12 addi x7,x3,-9 or x4,x7,x2 and x5,x3,x4 add x5,x5,x4 beq x5,x7,0x48 I want to get the assembled instructions in hex. format to load…
Dan
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How can I put the instruction code of the main() or _start() function first in instruction memory when using "riscv32/64-unknown-elf-gcc"?

I designed RISCV32IM processor, and i used "riscv32/64-unknown-elf-gcc" to generate code for test. I am testing on a system without an OS, and when I use the compile option (-O0) below, I am reluctant because there is a lot of unnecessary code…
doldooly
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Problems using risc-v timer interrupts and simulating with spike

I'm trying to make a timer interrupt, I have the following risc-v_tools installed riscv64-unknown-elf-gcc toolchain, spike simulate and pk . this is my code: #define MTIME *((volatile uint64_t *) 0x02000000 + 0xbff8) #define MTIMECMP …
Juan Romero
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2 answers

How to load a word from an immediate 32 bit address in risc-v assembly?

I want to load a word from 0x0200bff8 address into t1 register. I tried the following; lui t0, 0x0200b; // Write Upper 20 bits into t0 lw t1, 0xff8(t0); //fetch a word from address in t0 offsetted by 0xff8 (12 bits) I thought its syntactically…
RRON
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