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Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

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Vivado Synthesis hangs in Docker container spawned by Jenkins

I'm attempting to move our large FPGA build into a Jenkins CI environment, but the build hangs at the end of synthesis when run in a Docker container spawned by Jenkins. I've attempted to replicate the environment that Jenkins is creating, but when…
harkness
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How to initialize contents of inferred Block RAM (BRAM) in Verilog

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as below: module ram( input clock, // System clock input we, // When high RAM sets data in input lines to given address …
Paulo C
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Type conversion in VHDL: real to integer - Is the rounding mode specified?

While debugging the handling of user defined physical types in Vivado (read more), I found a different behavior for type conversions from real to integer. Here is my example code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use …
Paebbels
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Error "procedural assignment to a non-register result is not permitted"

I'm getting the error [Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult.v":29] What am i doing wrong? module lpm_mult ( dataa, datab, // multiplicand,multiplier sum, // partial…
Helyx
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Vivado, Zynq, BRAM Controller, Narrow AXI burst option

Consider a simple system with PS (Processor system) with enabled AXI3 Master, connected to AXI4 Interconnect connected to BRAM Controller that has access to BRAM memory. What is the meaning of AXI Narrow Bursts? How do i define or consider what is…
CJC
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AXI Protocol, difference between secure and non-secure transactions

Just wanted to ask, what is the difference between secure and non-secure transactions when it comes to AXI bus transactions? What are the performance implications of either transaction?
CJC
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How to syntax check VHDL in Vivado without complete synthesis

What's the simplest way to syntax-check my VHDL in Vivado without running through a full synthesis? Sometimes I code many inter-related modules at once, and would like to quickly find naming errors, missing semi-colons, port omissions, etc. The…
edj
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Using the clock on BASYS 3

I want to use the clock of the BASYS 3 for my project. When I search for the constraint of the Project I found the following code: set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name…
user6210457
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how to implement FPGA coprocessing with C/C++ on zynq 7020?

I'm studying vivadoHLS, and the tutorial u871 has introduced how to use HLS, and optimize my C/C++ code. But I want to know how to load them into my board zynq 7020, let it run on board. What I want to implement is : The host (CPU on board) calls…
happybunnie_wy
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Can I use Vivado block design clock frequencies in my VHDL?

I'm building a design in Vivado and am wondering if I can use the block diagram clock frequencies in my HDL. I want to take the FREQ_HZ that the block diagram knows about and propagates as part of DRC, and feed it into my custom IP blocks (using a…
blueshift
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Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?

I have been unable to find an answer, possibly due to me being unable to put specific enough nomenclature on the involved processes. I use Vitis HLS to synthesize designs where one call of the main function is one clock cycle long, being pipelined…
PhilMasteG
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What files to check into git in a Vivado Project file?

I have a vivado project directory that I want to check into git. I have all my VHDL source files one directory up from the "vivado project" directory under "../hdl/". My guess is that I only need to check in: git add ./hdl/*.vhd git add…
pico
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Vivado infers incorrect FREQ_HZ for AXI busses to my module

I'm working on a design in Vivado. My top level design is a block diagram. The block diagram has IP blocks and my Verilog RTL modules. Whenever I change my main module and Verilog updates the block diagram, it always incorrectly infers the clock…
Ethan Reesor
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what is the main difference between project mode and non project mode in vivado?

And when the synthesis is completed i am getting many files like .fw, .mcs, .prm along with .bit file, and can we dump those other files other than .bit file into FPGA? Which one is more advantageous project mode or non project mode? Coding is done…
vlsi_user
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How to pass arguments to tcl script in Vivado GUI tcl console

I am trying to execute a tcl script in Vivado GUI Tcl Console and my script takes an argument to decide which type of run (synth, impl, bitgen etc.) has to be configured. I know that, using -tclargs one could pass arguments if the script is executed…
Vinay Madapura
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