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I'm building a design in Vivado and am wondering if I can use the block diagram clock frequencies in my HDL.

I want to take the FREQ_HZ that the block diagram knows about and propagates as part of DRC, and feed it into my custom IP blocks (using a VHDL generic). This is so that I can do things like set up internal counts to generate delays in microseconds, baud rates, etc.

I could do this with a manual Customisation Parameter, but that would need manual maintaining and be prone to error.

blueshift
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  • This question doesn't appear to present a specific VHDL programming question. –  Nov 18 '14 at 13:49
  • It probably applies similarly to Verilog, but I am using and familiar only with VHDL. But if you mean this is more of a vendor tool question - yes it is. – blueshift Nov 19 '14 at 00:49

1 Answers1

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I think TCL might be your only option here. Make a TCL script which runs as a part of your build process, and copy the FREQ_HZ attribute to your generic.

Timmy Brolin
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