How to syntax check VHDL in Vivado without complete synthesis

Question

What's the simplest way to syntax-check my VHDL in Vivado without running through a full synthesis?

Sometimes I code many inter-related modules at once, and would like to quickly find naming errors, missing semi-colons, port omissions, etc. The advice I've read is to run synthesis, but that takes longer than I need for just a syntax check. I've observed that syntax errors will usually cause synthesis to abort within the first minute or so, so my workaround is to run synthesis and abort it manually after about a minute.

Vivado editor has in-built syntax checking which marks syntax errors, not declared signals, missing semi-colon etc., at least from 2017 onwards. For port omissions and errors in sub-modules, simulation should do the job. — Vinay Madapura, Mar 13 '18 at 15:37
Why the downvote? Conceptually, this is like a compile and link question. I don't want to run the code (requiring a link), I just want to get through a clean compile first. — edj, Mar 13 '18 at 17:16
There's also the `check_syntax` command when not using the Vivado editor. See ug835 Vivado TCL Command Reference Guide. — , Mar 13 '18 at 20:43
That's what I was looking for. Even when using Vivado, "check_syntax" works in the TCL command window. Thanks! — edj, Mar 13 '18 at 22:47
@VinayMadapura The internal syntax checker of Vivado is not correct in all cases. It's just an estimation of possible problems. It's also not using the same language front end as the simulator or synthesizer. Otherwise all three would report the same problems ... — Paebbels, Mar 17 '18 at 15:16

score 4 · Accepted Answer · answered Mar 13 '18 at 22:50

4

In the Vivado Tcl Console window, the check_syntax command performs a fast syntax check, catches typos, missing semi-colons, etc.

answered Mar 13 '18 at 22:50

edj

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score 1 · Answer 2 · answered Mar 17 '18 at 15:19

Vivado offers an elaboration step before synthesis. This is the lightweight version of y synthesis by just reading all sources and creating a design model based on the language without optimizations and transformations.

A pure syntax check per file is not enough in many cases. You also want to know if certain identifiers exist and if types are matching. Therefore, an elaboration is needed.

(If you never have heard of that step: VHDL compiling has 2 steps: Analysis and Elaboration. Think of elaboration like of linking in ANSI C.)

How to syntax check VHDL in Vivado without complete synthesis

2 Answers2