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Questions tagged [xilinx-ise]

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

291 questions
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Type conversion in VHDL: real to integer - Is the rounding mode specified?

While debugging the handling of user defined physical types in Vivado (read more), I found a different behavior for type conversions from real to integer. Here is my example code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use …
Paebbels
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Where does the Xilinx TCL shell emit the results?

I'm trying to develop a Python based wrapper around the Xilinx ISE TCL shell xtclsh.exe. If it works, I'll add support for other shells like PlanAhead or Vivado ... So what's the big picture? I have a list of VHDL source files, which form an IP…
Paebbels
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Alternative method for creating low clock frequencies in VHDL

In the past I asked a question about resets, and how to divide a high clock frequency down to a series of lower clock square wave frequencies, where each output is a harmonic of one another e.g. the first output is 10 Hz, second is 20 Hz etc. I…
davidhood2
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Verify Parameters in Verilog

I have created a module which accepts a single parameter specifying the byte width of the module's data lines. It looks something like: module wrapper# ( parameter DATA_BYTE_WIDTH = 1 ) ( din, dout, .. ); localparam DATA_BIT_WIDTH =…
Chris
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Warning: VC++ 2008 runtime libraries are not installed. Xilinx

I installed the ISE from Xilinx to my windows PC and it ended up very bad. It isn't working, since when I try to run it, the next message appears Warning: VC++ 2008 runtime libraries are not installed. Please install the runtime libraries by running…
Miguel Fernández
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Connecting a STD_LOGIC to a one bit STD_LOGIC_VECTOR

I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard. The problem is that it created a write enable signal (wea) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch: Line ###: Type error near…
mark_infinite
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Illegal syntax for subtype indication VHDL200X

I am trying to create a "dynamic" 2D array which I can set with generics in my entity. I followed the example in…
MVT
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Increasing the speed of Xilinx ISim simulation

I have a large ISim design for Spartan-6 using about 6 of the Spartan-6 FPGA IP cores. It needs to run for a simulation time of 13 seconds, but at present takes 40 seconds to run a simulation time of 1 ms. During the 13 seconds it will also write…
davidhood2
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Copying ISim results as strings/text

I'm creating a VHDL project, and using ISim to simulate beforehand - which is all fine. However, my results use fixed point - and although Isim can represent its signals as a range of radix's, unsurprisingly, fixed point decimal isn't one of…
davidhood2
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Finding Maximum delay through FPGA design from a VHDL code written in Xilinx software

i am working on AES code and my aim is to create an architecture which will give the fastest performance. hence i need to determine the delay from the time input is given and the final output is obtained. the design is to be implemented on fpga. i…
Nilima Parmar
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Implementing hardware that divides an 8 bit number by 3 (11) in binary

I want to create a schematic that divides any 8-bit number by 3, on a Xilinx device in case that matters. For example, hardware takes two inputs (111101) and (11) and returns the division of two numbers which is 010100. I don't need to worry about…
user19076994
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How do you select a range of bits from an expression of registers?

I am trying to take the average of 8 8-bit registers. I was able to do it structurally, by having four 8-> 9-bit adders, two 9-> 10 bit adder, and one 10-> 11-bit adder. This works correctly; however, I was curious if there is a better way/ more…
bitbytten
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ISE Design Suite 14.7: ISE® Spartan®-6 Virtual Machine (VM) for Windows 10

I installed Xilinx ISE 14.7 on Windows 10. When I try to open Project Navigator it opens in a Linux Virtual Machine (VM). It means Xilinx setup installs a VM environment in windows 10. Is it possible to install ISE Design Suit in windows 10 instead…
Chand Baba
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VHDL Warning Xst:1293 FF/Latch has a constant value of 0

None of the answer on the internet worked for me as I am a beginner in VHDL. I am making a password interface in vhdl with pushbuttons and LEDs. My program simulates correctly as expected. Basically, I want LEDs to blink when entering wrong…
Pankaj Kumar
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reading FPGA's block RAM from pc

I am using Xilinx ISE 14.7 synthesizer. I am able to initialize my BRAM with a .coe file and access it. Also I can update it with new .mem file using data2mem tool and update my bit file. Here I have configured it as ROM. My problem is, I don't know…
M.Navidi
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