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I have a large ISim design for Spartan-6 using about 6 of the Spartan-6 FPGA IP cores. It needs to run for a simulation time of 13 seconds, but at present takes 40 seconds to run a simulation time of 1 ms. During the 13 seconds it will also write 480000 24 bit std_logic_vectors to a text file.

This equates to running time of 144 hours to run the entire simulation (almost a week!).

Is there a way, for example, of increasing the step size or turning off the settings for waveform plotting etc, or any other settings I can use to increase the simulation speed?

So far I have tried not plotting the waveform, but it doesn't seem to actually increase the speed.

Thanks very much

davidhood2
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1 Answers1

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Yes adding signals to the waveform slowes every simulator down... but running such long simulations always create GiB of data and take hours or days.

You could check your code and:

  • improve sensitivity lists to reduce calculation cycles
  • some IP cores have a fast simulation mode which can be enabled by a generic parameter.

But in general there is only one solution: use another simulator. Especially one with optimization. (Can be disabled or restricted in free editions) E.g.:

  • GHDL - is open source and quite fast
  • QuestaSim / ModelSim
    ModelSim is for example included in Altera Quartus Prime (WebPack) for free as Starter Edition.
  • Active-HDL
    Active-HDL Student Edition is free to use. Alteratively, it's included in Lattice Diamond.

P.S. 40 sec for 1 ms (25 us per second) is very fast. My integration simulations usually calculate 20 ns per second. So you are 1000x faster)

Paebbels
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  • Will the Xilinx IP cores simulate in a different simulator? – davidhood2 May 01 '16 at 19:58
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    What's the IP core name? Is it a netlist or source code? Xilinx primitives can be simulated with other simulators. ISE can compile its primitives for other simulators like QuestaSim or ModelSim. The can be compiled for GHDL too. Complex IP cores as netlist are more difficult but some of the can be generated with a simulation model (a large VHDL file). This file can be used as an input to other simulators. – Paebbels May 01 '16 at 20:03
  • This should work in other simulators. So the question remains, why do you need 13 seconds? No testbench should run so long. If you're calculating results put it onto the FPGA it's quite faster => hardware accelerated simulation. – Paebbels May 01 '16 at 20:20
  • It is a graphics ray tracer for a 600x800 screen. In the presence of deadline, I do not have time to get it fully linked up on the FPGA with other parts. My plan was instead to simulate a frame into a text file and display it... – davidhood2 May 01 '16 at 20:32
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    So you need to decide: wait a week or implement it on FPGA in less than one week ... What if your simulation fails? Wait another week or start to implement the design? How long are you going to watch your simulation die until you decide to go the hard way and implement it? I'm a (HDL) designer who has always a sledge-hammer within reach (ChipScope, embedded 8-bit CPU for test control or Gigabit Ethernet to streamout data / trace) to crack the nut / bug. – Paebbels May 01 '16 at 20:47
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    Then set X_size and Y_size to 80 and 60 for the simulation, and bring it down to a barely tolerable hour or so. –  May 02 '16 at 08:38
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    I've allocated this as the answer because @Paebbels recommendation on using hardware is what I opted for - I instantiated a UART core, ran it in hardware and collected the results using PuTTY in a whole 14 seconds (rather than 144 hours). Although I know its not conventional, I would also like to thank Paebbels, Brian Drummon & others aside for ad-infinitum patience & help on SO over the past 9 months, without whom my undergrad project would most likely have failed a long time ago....Thanks again. – davidhood2 May 04 '16 at 15:15